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* svga: check for null fs pointer in update_samplers()Brian Paul2017-12-281-1/+1
| | | | | | | | This can happen when there's no active fragment shader, such as when using transform feedback. This wasn't hit by any Piglit test but is hit by Daniel Rákos' Nature demo. VMware bug 2026189. Reviewed-by: Charmaine Lee <[email protected]>
* svga: move variant->fs_shadow_compare_units assignmentBrian Paul2017-12-271-2/+2
| | | | | | | Fixes a crash since the variant object isn't allocated until later in the function. Not sure how this got through. Reviewed-by: Charmaine Lee <[email protected]>
* radeonsi: make use of ac_init_exec_full_mask()Samuel Pitoiset2017-12-271-11/+3
| | | | | | | Similar to si_init_exec_full_mask(). Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* svga: use tgsi_util_get_shadow_ref_src_index() in a couple placeBrian Paul2017-12-261-22/+7
| | | | | | | No piglit changes. Reviewed-by: Neha Bhende <[email protected]> Reviewed-by: Charmaine Lee <[email protected]>
* svga: fix TGSI_TEXTURE_SHADOW1D coordinate selectionBrian Paul2017-12-261-3/+1
| | | | | | | Fixes about 24 Piglit tex-miplevel-selection tests. Reviewed-by: Neha Bhende <[email protected]> Reviewed-by: Charmaine Lee <[email protected]>
* svga: fix shadow comparison failuresBrian Paul2017-12-265-36/+78
| | | | | | | | | | | | | | In some cases, We do shadow comparison cases in the fragment shader instead of with texture sampler state. But when we do so, we must disable the shadow comparison test in the sampler state. As it was, we were doing the comparison twice, which resulted in nonsense. Also, we had the texcoord and texel value swapped in the comparison instruction. Fixes about 38 Piglit tex-miplevel-selection tests. Reviewed-by: Neha Bhende <[email protected]> Reviewed-by: Charmaine Lee <[email protected]>
* r600: fix atomic counter index mode getting emitted on pre-caymanDave Airlie2017-12-271-1/+1
| | | | | | | This is a regression since I added cayman atomic support, not sure it fixes anything, but the shader dumps look better. Signed-off-by: Dave Airlie <[email protected]>
* radv/radeonsi: set dcc min uncompressed properly for APUs.Dave Airlie2017-12-271-0/+9
| | | | | | | This is ported from amdvlk. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* amd/common/radv/radeonsi: use register defines for dcc block sizes.Dave Airlie2017-12-271-3/+3
| | | | | | | | These are just taken from amdvlk, we probably knew these already, but may as well port them now. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radeonsi: don't use fast color clear for small images even on APUsMarek Olšák2017-12-251-5/+4
| | | | | | | | | | Increase the limit and handle non-square images better. This makes glxgears 20% faster on APUs, and a little more on dGPUs. We all use and love glxgears. Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: set PNT_SPRITE_ENA = point_quad_rasterizationMarek Olšák2017-12-251-1/+1
| | | | This is based on how nvc0 translates the state.
* gallium/util: add util_num_layers helperMarek Olšák2017-12-254-10/+10
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* freedreno: set missing internal_format when importing textureIlia Mirkin2017-12-221-0/+1
| | | | | | | Fixes running piglits without -fbo. Probably lots of other stuff too. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* amd/common: add ac_export_mrt_z() helperSamuel Pitoiset2017-12-221-60/+1
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: pass the family to ac_llvm_context_init()Samuel Pitoiset2017-12-221-1/+2
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* gm107/ir: use lane 0 for manual textureGrad handlingIlia Mirkin2017-12-221-21/+34
| | | | | | | | | | This is parallel to the pre-SM50 change which does this. Adjusts the shuffles / quadops to make the values correct relative to lane 0, and then splat the results to all lanes for the final move into the target register. Signed-off-by: Ilia Mirkin <[email protected]> Tested-By: Karol Herbst <[email protected]>
* nvc0/ir: change textureGrad to always use lane 0 as the tex originIlia Mirkin2017-12-191-14/+46
| | | | | | | | | | | | | | | | | | | Thanks to Karol Herbst for the debugging / tracing work that led to this change. Move to using lane 0 as the "work" lane for the texture. It is unclear why this helps, as that computation should be identical to doing it in the "correct" lane with the properly adjusted quadops. In order to be able to use the lane 0 result, we also have to ensure that lane 0 contains the proper array/indirect/shadow values. This applies to Fermi and Kepler. Maxwell+ may or may not need fixing, but that lowering logic is separate. Fixes KHR-GL45.texture_cube_map_array.sampling Signed-off-by: Ilia Mirkin <[email protected]>
* broadcom/vc5: Add missing setting of the UIF XOR disable flag in textures.Eric Anholt2017-12-191-0/+3
| | | | | Most piglit textures happened to work out by RGBW not changing in that bit, but it did cause failures in RGBA16F fbo-generatemipmap-formats.
* broadcom/vc5: Clean up the comment and code around level 0 UIF.Eric Anholt2017-12-191-14/+10
| | | | | I wrote this early in driver development, and our UIF handling is much better now.
* broadcom/vc5: Simplify the tiling calculations.Eric Anholt2017-12-191-49/+11
| | | | | The mb_tile_layout table was just the utile_w/h times two, so reuse the utile code instead.
* broadcom/vc5: Return the depth in all components of depth textures.Eric Anholt2017-12-191-6/+6
| | | | | | Apparently gallium's u_blitter wants depth from at least the .z component, and other swizzling appears to apply on top of that. Fixes fbo-generatemipmap-formats failures with depth formats.
* broadcom/vc5: Enable decompressing RGTC for desktop GL support.Eric Anholt2017-12-191-1/+1
| | | | This matches freedreno's behavior.
* broadcom/vc5: Use u_transfer_helper for MSAA mappings.Eric Anholt2017-12-192-98/+6
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* broadcom/vc5: Start adding support for rendering to Z32F_S8X24_UINT.Eric Anholt2017-12-193-5/+94
| | | | | | | | | | There may be some more RCL work to be done (I think I need to split my Z/S stores when doing separate stencil), but this gets piglit's "texwrap GL_ARB_depth_buffer_float" working. v2: Unwrap the z32f_wrapper before calling the helper, rather than having the helper have a callback. v3: Rebase on Rob Clark's u_transfer_helper instead
* freedreno: add debug flag to force high priority contextRob Clark2017-12-193-1/+5
| | | | | | | Mainly for testing, FD_MESA_DEBUG=hiprio will force high priority contexts. Signed-off-by: Rob Clark <[email protected]>
* freedreno: context priority supportRob Clark2017-12-193-2/+20
| | | | | | | For devices (and kernels) which support different priority ringbuffers, expose context priority support. Signed-off-by: Rob Clark <[email protected]>
* gallium: plumb context priority through to driverRob Clark2017-12-1916-0/+16
| | | | | | | | Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Andres Rodriguez <[email protected]> Reviewed-by: Wladimir J. van der Laan <[email protected]>
* freedreno/ir3: handle VTXID_BASE for indirect drawsRob Clark2017-12-191-2/+41
| | | | | | | | | Need to do some gymnastics to copy the parameter from the indirect parameters buffer to uniform so shader sees the correct base-vertex-id. Fixes ./bin/arb_draw_indirect-vertexid on a5xx and probably a4xx too. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: add ctx->mem_to_mem()Rob Clark2017-12-194-14/+49
| | | | | | | | For dealing with indirect-draw + gl_VertexID, we'll introduce another case where we need to use CP_MEM_TO_MEM. Rather than adding more if(a5xx)/else make this a ctx vfunc. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: use vertex_id_zero_baseRob Clark2017-12-192-20/+1
| | | | | | | | | | | | | Cmdstream traces from blob make it clear that the blob driver dev's *think* a5xx has a real (non-zero-based) vtxid. But reality claims differently. Fixes ./bin/gl-3.2-basevertex-vertexid and probably others. This means draw-indirect is going to need some gymnastics to copy base-vertex into uniform. (a4xx probably needs that too.) Signed-off-by: Rob Clark <[email protected]>
* r600: clear compressed flags in image state on unbind.Dave Airlie2017-12-191-0/+2
| | | | | | | | | If we aren't binding an image, clear the compressed flags. This fixes a segfault seen with an apitrace. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104331 Signed-off-by: Dave Airlie <[email protected]>
* swr: Account for index_bias in offsetsGeorge Kyriazis2017-12-181-3/+3
| | | | | | | | | | When calculating buffer offsets for client buffers account for info.index_bias. Fixes the follow piglit tests: arb_draw_elements_base_vertex-drawelements-user_varrays arb_draw_elements_base_vertex-negative-index-user_varrays Reviewed-By: Bruce Cherniak <[email protected]>
* r600: only reported tgsi ir compute support on evergreen+Dave Airlie2017-12-181-1/+3
| | | | | | This fixes a crash on r600/r700. Signed-off-by: Dave Airlie <[email protected]>
* amd/common: add ac_vgt_gs_mode() helperSamuel Pitoiset2017-12-181-29/+3
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: add ac_get_cb_shader_mask() helperSamuel Pitoiset2017-12-181-33/+1
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* r600: export robust buffer accessDave Airlie2017-12-181-1/+1
| | | | Signed-off-by: Dave Airlie <[email protected]>
* r600: export GLSL 430Dave Airlie2017-12-181-1/+1
| | | | Signed-off-by: Dave Airlie <[email protected]>
* r600/cs: add compute support to capsDave Airlie2017-12-181-2/+2
| | | | Signed-off-by: Dave Airlie <[email protected]>
* r600: always flush between gfx and computeDave Airlie2017-12-185-0/+21
| | | | | | | | This is in no way optimal, but there seems to be some problems mixing at the moment, lots of hangs, it is possible, just need to figure out more magic. Signed-off-by: Dave Airlie <[email protected]>
* r600: fix unused variable warningDave Airlie2017-12-181-1/+0
| | | | Signed-off-by: Dave Airlie <[email protected]>
* freedreno/a5xx: add a5xx blitterRob Clark2017-12-178-1/+498
| | | | | | FD_MESA_DEBUG=noblit to disable Signed-off-by: Rob Clark <[email protected]>
* freedreno: add generic blitterRob Clark2017-12-177-2/+161
| | | | | | | Basically a clone of util_blitter_blit() but with special handling to blit PIPE_BUFFER as a PIPE_TEXTURE_1D. Signed-off-by: Rob Clark <[email protected]>
* freedreno: add non-draw batches for compute/blitRob Clark2017-12-1712-32/+82
| | | | | | | | | Get rid of "gmem" (ie. tiling) ringbuffer, and just emit setup commands directly to "draw" ringbuffer for compute (and in future for blits not using the 3d pipe). This way we can have a simple flat cmdstream buffer and bypass setup related to 3d pipe. Signed-off-by: Rob Clark <[email protected]>
* freedreno: track staging and shadow perf ctrs for the HUDRob Clark2017-12-175-0/+16
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: staging upload transfersRob Clark2017-12-173-43/+135
| | | | | | | | | | In the busy && !needs_flush case, we can support a DISCARD_RANGE upload using a staging buffer. This is a bit different from the case of mid- batch uploads which require us to shadow the whole resource (because later draws in an earlier tile happen before earlier draws in a later tile). Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2017-12-177-63/+334
| | | | Signed-off-by: Rob Clark <[email protected]>
* radeonsi: don't call force_dcc_off for buffersMarek Olšák2017-12-161-1/+1
| | | | | | | | This was undefined yet harmless behavior in LLVM. Not anymore - it causes a hang now. Cc: 17.3 <[email protected]> Tested-by: Michel Dänzer <[email protected]>
* radeon/uvd: add and manage render picture listBoyuan Zhang2017-12-151-4/+25
| | | | | | | | | | | | | | | | Create a list in decoder to store all render picture buffer pointers that currently being used in reference picture lists. During get message buffer call, check each pointer in render_pic_list[] within given pic->ref[] list, remove pointer that no longer being used by pic->ref[]. Then add current render surface pointer to the render_pic_list[] and assign the associated index to result.curr_idx. As a result, result.curr_idx will have the correct index to represent the current render picture, instead of the previous increamenting values. Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/vcn: add and manage render picture listBoyuan Zhang2017-12-151-4/+24
| | | | | | | | | | | | | | | | Create a list in decoder to store all render picture buffer pointers that currently being used in reference picture lists. During get message buffer call, check each pointer in render_pic_list[] within given pic->ref[] list, remove pointer that no longer being used by pic->ref[]. Then add current render surface pointer to the render_pic_list[] and assign the associated index to result.curr_idx. As a result, result.curr_idx will have the correct index to represent the current render picture, instead of the previous increamenting values. Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/vce: determine idr by pic typeBoyuan Zhang2017-12-151-1/+1
| | | | | | | | | Vaapi encode interface provides idr frame flags, where omx interface doesn't. Therefore, change to use picture type to determine idr frame, which will work for both interfaces. Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]>
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