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* softpipe: tie in new code path for lod evaluationGert Wollny2019-05-012-46/+21
| | | | | | | | | This enables the use of explicit gradients. Also remove an unused parameter when changing the interfaces. Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* softpipe: Move selection of shadow values up and clean parameter listGert Wollny2019-05-011-29/+43
| | | | | | | | | The shadow evaluation compare parameter is stored in different locations, depending on the texture type. Move the values to a common location free the lod storage and to be able to reduce the number of parameters. Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* softpipe: Pipe gather_comp through from st_tgsi_get_samplesGert Wollny2019-05-012-5/+18
| | | | | | | | The value is stored in the lod components and this will be overwritten when swithcing to the new code path. Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* softpipe: Prepare handling explicit gradientsGert Wollny2019-05-013-1/+42
| | | | | | | This only adds corde that is not yet enabled. Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* softpipe: Factor gradient evaluation out of the lambda evaluationGert Wollny2019-05-011-19/+119
| | | | | | | this is useful when we want to use explicit gradients. Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* radeonsi/nir: call radeonsi nir opts before the scan passTimothy Arceri2019-05-012-0/+2
| | | | | | | | | | | | | | Some of the opts are not called in the general optimastion loop in the state trackers glsl -> nir conversion. We need to call the radeonsi specific optimisation once before scanning over the nir otherwise we can end up gathering info on code that is later removed. Fixes an assert in the piglit test: ./bin/varying-struct-centroid_gles3 Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/nir: create si_nir_opts() helperTimothy Arceri2019-05-012-36/+43
| | | | | | We will make use of this in the following commit. Reviewed-by: Marek Olšák <[email protected]>
* swr/rast: early exit on empty triangle maskAlok Hota2019-04-301-0/+6
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: add guards for cpuid on LinuxAlok Hota2019-04-301-0/+2
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: add flat shadingAlok Hota2019-04-301-0/+13
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: add SWR_STATIC_ASSERT() macroAlok Hota2019-04-301-1/+8
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: update guardband rects at draw setupAlok Hota2019-04-301-2/+3
| | | | | | It's dependent on other state fields Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: add more llvm intrinsicsAlok Hota2019-04-301-0/+3
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* radeonsi: implement resource_get_infoJulien Isorce2019-04-301-8/+35
| | | | | | | | Re-use existing si_texture_get_offset. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110443 Signed-off-by: Julien Isorce <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* iris: Enable fast clear colors on gen11.Rafael Antognolli2019-04-301-3/+0
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Update the surface state clear color address when available.Rafael Antognolli2019-04-301-1/+9
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Use the linear version of the surface format during fast clears.Rafael Antognolli2019-04-301-1/+7
| | | | | | | | | | | | | | Newer gens (> 9) will start doing the linear -> sRGB conversion of the clear color for us, if we use a sRGB surface format. So let's make sure that doesn't happen and keep the same semantics as before. Even though the hardware could convert the clear color for us during fast clear, that converted color is only used for sampling. For resolve, the original color would be used (without the conversion). So we convert it ourselves and the same converted color gets used for both sampling and resolving, simplifying the whole logic. Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Support sRGB fast clears even if the colorspaces differ.Rafael Antognolli2019-04-302-4/+8
| | | | | | | | | | | | | | We were disabling fast clears if the view format had a different colorspace than the resource format (sRGB vs linear or vice-versa). But we actually support them if we use the view format to decide if we should encode the clear color into sRGB colorspace. Also add a missing linear -> sRGB surface format conversion (we don't want the clear color to be encoded to sRGB again during resolve). v2: Do not track sRGB colorspace during fast clears (Nanley). Reviewed-by: Kenneth Graunke <[email protected]>
* panfrost/ci: Initial commitTomeu Vizoso2019-04-308-0/+3248
| | | | | | | | | | | | | | | | | | | | | | | | | | | | These files implement running almost all of deqp-gles2 on Chomebooks of the rk3399-gru-kevin type in Collabora's LAVA lab. The approach follows what is currently being used for virglrenderer, but scheduling the actual test jobs via LAVA. We start by building a container in Docker that contains a suitable rootfs and kernel for the DUT, deqp and all dependencies for building Mesa itself. The Mesa is built and the rootfs, deqp and Mesa are combined in a cpio ramdisk. A LAVA job is generated, submitted to LAVA and the results are processed by simply comparing them to the expectations that are stored in git. Any code that changes the expectations (hopefully tests are fixed) needs to also update the expectations file. The next step is adding support for other devices, possibly in other LAVA labs. In order to use this, the repository has to be configured to run the gitlab-ci.yaml file from the panfrost/ci dir, and a LAVA token needs to be setup. Signed-off-by: Tomeu Vizoso <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* iris: Do not advertise multisampled image load/store.Rafael Antognolli2019-04-291-0/+5
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* freedreno/a6xx: pre-bake UBWC flags in texture-viewRob Clark2019-04-292-3/+5
| | | | | | Small cleanup. No need to defer this to emit time. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: small texture emit cleanupRob Clark2019-04-294-37/+34
| | | | | | | | | | | Prep work for fb_read (blend_equation_advanced) Switch to using 'enum pipe_shader_type' everywhere, and (optional, in non-cache / slowpath case) pass ctx instead of image/ssbo state. In the fb_read case we also need to access the framebuffer state, so having the ctx simplifies things. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: switch fragcoord to sysvalRob Clark2019-04-291-0/+1
| | | | | | Because who are we kidding... it is a sysval. Signed-off-by: Rob Clark <[email protected]>
* delete autotools .gitignore filesEric Engestrom2019-04-2910-26/+0
| | | | | | | | One special case, `src/util/xmlpool/.gitignore` is not entirely deleted, as `xmlpool.pot` still gets generated (eg. by `ninja xmlpool-pot`). Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* iris: Only enable GL_AMD_depth_clamp_separate on Gen9+Kenneth Graunke2019-04-291-1/+1
| | | | | The hardware feature is new as of Gen9+. I accidentally enabled it on Gen8.
* iris: Set XY Clipping correctly.Kenneth Graunke2019-04-294-2/+67
| | | | | | | | | | I was setting it based off a pipe_rasterizer_state field that appears to be entirely dead outside of the draw module respecting it. I should be setting it when the primitive type reaching the SF is neither points nor lines. This is, unfortunately, rather dirty, as we have to look at the rasterizer state, the geometry shader state, the tessellation evaluation shader state, and the primitive type...
* swr: support NULL-resourcesErik Faye-Lund2019-04-291-24/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | It's legal for a buffer-object to have a NULL-resource, but let's just skip over it, as there's nothing to do. This patch switches the order of the conditionals in swr_update_derived, so the logic becomes a bit more straight forward: if (is_user_buffer) ... else if (resource) ... else ... ...instead of this: if (!is_user_buffer) if (resource) ... else ... else ... Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Alok Hota <[email protected]>
* nouveau: support NULL-resourcesErik Faye-Lund2019-04-292-3/+10
| | | | | | | | It's legal for a buffer-object to have a NULL-resource, but let's just skip over it, as there's nothing to do. Signed-off-by: Erik Faye-Lund <[email protected]> Acked-by: Karol Herbst <[email protected]>
* i915: support NULL-resourcesErik Faye-Lund2019-04-291-2/+5
| | | | | | | It's legal for a buffer-object to have a NULL-resource, but let's just skip over it, as there's nothing to do. Signed-off-by: Erik Faye-Lund <[email protected]>
* lima/ppir: fix pointer referenced after a freePatrick Lerda2019-04-291-1/+2
| | | | | | | | | Issue detected by valgrind. Fixes: 92d7ca4b1cd ("gallium: add lima driver") Signed-off-by: Patrick Lerda <[email protected]> Reviewed-by: Qiang Yu <[email protected]>
* lima/ppir: Add gl_FragCoord handlingAndreas Baierl2019-04-297-2/+33
| | | | | | | | | Treat gl_FragCoord variable as a system value and lower the w component with a nir pass. Add the necessary bits for correct codegen. Signed-off-by: Andreas Baierl <[email protected]> Reviewed-by: Qiang Yu <[email protected]>
* panfrost: Workaround -bshadow regressionAlyssa Rosenzweig2019-04-281-1/+8
| | | | | | | I have *no* idea what's happening here, but let's not regress an app that used to work in the mean time while we're figuring it out.. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Safety check immediate precision degradationsAlyssa Rosenzweig2019-04-281-1/+14
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Use fp32 (not fp16) varyingsAlyssa Rosenzweig2019-04-281-4/+4
| | | | | | | | | | In a perfect world, we'd use fp16 varyings for mediump and fp32 for highp, allowing us to get a performance win without sacrificing conformance. Unfortunately, we're not there (yet), so it's better we assume always fp32 than always fp16 to avoid artefacts / breaking a lot of deqp. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: imov workaroundAlyssa Rosenzweig2019-04-281-6/+27
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Fix tex propogationAlyssa Rosenzweig2019-04-281-7/+22
| | | | | | Unbreaks mpv. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Fix regressions in -bjellyfishAlyssa Rosenzweig2019-04-281-3/+7
| | | | | | | | | Two fixes here, one is that we tried to copyprop non-strictly-SSA values which was bound to fly in our face. The other was peeling back the imov workaround.. Turns out we still need that. More research is needed still, but let's not regress real apps. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Only copyprop without an outmodAlyssa Rosenzweig2019-04-281-0/+1
| | | | | | | With an outmod, we would need to propagate that through, which is for future work. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* Revert "panfrost/midgard: Extend copy propagation pass"Alyssa Rosenzweig2019-04-281-48/+8
| | | | | | | | | Fixes: commit b53b4573c3f0571253672e44ce7d6310d9f987bf. Optimization gone wrong. In the future, we should try this again (it's a net win if implemented right), but at the moment this just regresses. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* iris: Fix zeroing of transform feedback offsets in strange cases.Kenneth Graunke2019-04-272-4/+18
| | | | | | | | | | | | | | | | | | | | Some of the dEQP.functional.transform_feedback tests end up doing the following sequence of operations: 1. BeginTransformFeedback 2. PauseTransformFeedback 3. Draw 4. ResumeTransformFeedback At step 1, we'd pack 3DSTATE_SO_BUFFER commands saying to zero the SO_WRITE_OFFSET registers. At step 2, we disable streamout, so step 3 doesn't bother emitting those commands. Then, step 4 re-packs new 3DSTATE_SO_BUFFER commands with offset = 0xFFFFFFFF, saying to continue appending at the existing offset. This loads the value from the BO as the offsets - but we never actually zeroed it. So, just maintain a flag saying "we actually emitted the commands", and stomp offset back to zero until we emit some.
* vc4: Fall back to renderonly if the vc4 driver doesn't have v3d.Eric Anholt2019-04-261-1/+0
| | | | | | | I have a platform with vc4 display but V3D 4.x. We can fall back on kmsro's probing to bring up the v3d gallium driver. Acked-by: Rob Clark <[email protected]>
* radeonsi: don't ignore PIPE_FLUSH_ASYNCMarek Olšák2019-04-261-1/+1
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* Revert "v3d: Disable PIPE_CAP_BLIT_BASED_TEXTURE_TRANSFER."Eric Anholt2019-04-261-1/+9
| | | | | | This reverts commit ccce9409470c1053c40c822d759b9bd417062bc0, leaving a note as to why we had to (corruption in chromium, breaking some GLES3.1 tests).
* v3d: Don't try to update the shadow texture for separate stencil.Eric Anholt2019-04-261-1/+2
| | | | | | | | | | | There are two cases where v3d's sampler view's resource doesn't match the base's: shadow textures for sampling from raster, and pointing at the separate depth texture for z32f_s8x24. We only want to update shadow for the first case. Fixes dEQP-GLES31.functional.stencil_texturing.render.depth32f_stencil8_draw when run after the previous testcase.
* vc4: Use _mesa_hash_table_remove_key() where appropriate.Eric Anholt2019-04-261-12/+9
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* v3d: Use _mesa_hash_table_remove_key() where appropriate.Eric Anholt2019-04-261-13/+8
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* v3d: Apply the GFXH-930 workaround to the case where the VS loads attrs.Eric Anholt2019-04-261-0/+15
| | | | | | | We were emitting a dummy load for when the VS doesn't load any attributes, but we also need to emit a dummy load for when the render VS loads attributes but the binner VS doesn't. Fixes simulator assertion failures and GPU hangs on KHR-GLES31.core.texture_gather.\*
* v3d: Fill in the ignored segment size fields to appease new simulator.Eric Anholt2019-04-261-2/+4
| | | | | | We are assured that the input segment size field is ignored for !separate_segs mode, and now the simulator wants an in-range value set regardless of whether it's functionally ignored or not.
* swr/rast: enforce use of tile offsetsAlok Hota2019-04-264-0/+5
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: AVX512 support compiled in by defaultAlok Hota2019-04-2612-560/+333
| | | | | | | | | - Emulation of AVX512 built into SIMDLIB - Remove associated macros - Remove knobs controlling AVX512 and let emulation handle it - Refactor variable names for SIMD16 Reviewed-by: Bruce Cherniak <[email protected]>
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