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* r600: set mega fetch count to 16 for gs copy shaderDave Airlie2015-12-021-0/+1
* r600: increment ring index after emit vertex not before.Dave Airlie2015-12-021-18/+24
* r600: add alu + cf nop to copy shader on r600Dave Airlie2015-12-021-0/+10
* r600: SMX returns CONTEXT_DONE early workaroundDave Airlie2015-12-022-1/+13
* r600: do SQ flush ES ring rolling workaroundDave Airlie2015-12-023-1/+8
* nv50,nvc0: allow to create resources other than buffersSamuel Pitoiset2015-12-015-4/+9
* r600: workaround empty geom shader.Dave Airlie2015-12-011-0/+5
* r600: rv670 use at least 16es/gs threadsDave Airlie2015-12-011-4/+5
* r600: geometry shader gsvs itemsize workaroundDave Airlie2015-12-011-0/+20
* r600/shader: split address get out to a function.Dave Airlie2015-12-011-1/+6
* r600: move per-type settings into a switch statementDave Airlie2015-11-301-5/+13
* r600: split out common alu_writes pattern.Dave Airlie2015-11-301-7/+12
* r600/llvm: fix r600/llvm buildDave Airlie2015-11-301-1/+1
* r600: fixes for register definitions.Dave Airlie2015-11-301-3/+3
* r600: add missing register to initial stateDave Airlie2015-11-303-7/+15
* r600: define registers required for tessellationDave Airlie2015-11-302-27/+113
* r600: consolidate clip state updatesDave Airlie2015-11-302-17/+16
* nv50/ir: always display the opcode number for unknown instructionsSamuel Pitoiset2015-11-292-2/+2
* radeon: only suspend queries on flush if they haven't been suspended yetNicolai Hähnle2015-11-282-2/+9
* svga: Don't return value from void function.Jose Fonseca2015-11-271-1/+2
* freedreno/ir3: assign varying locations laterRob Clark2015-11-264-29/+37
* freedreno/ir3: use instr flag to mark unused instructionsRob Clark2015-11-264-14/+24
* freedreno/a4xx: rework vinterp/vpsreplRob Clark2015-11-261-12/+36
* freedreno/a3xx: rework vinterp/vpsreplRob Clark2015-11-261-12/+37
* radeon: use PIPE_DRIVER_QUERY_FLAG_DONT_LIST for perfcountersNicolai Hähnle2015-11-261-0/+2
* radeon: delay the generation of driver query names until first useNicolai Hähnle2015-11-263-104/+113
* radeonsi/compute: Use the compiler's COMPUTE_PGM_RSRC* register valuesTom Stellard2015-11-252-31/+7
* radeonsi: Rename si_shader::ls_rsrc{1,2} to si_shader::rsrc{1,2}Tom Stellard2015-11-253-6/+6
* radeonsi: implement AMD_performance_monitor for CIK+Nicolai Hähnle2015-11-2510-3/+1486
* radeon: scale query buffer size to result sizeNicolai Hähnle2015-11-251-1/+1
* radeonsi/sid: add performance counter registersNicolai Hähnle2015-11-251-0/+1013
* radeonsi/sid: add hardware constants for COPY_DATA packetNicolai Hähnle2015-11-251-0/+3
* radeon: extend CIK_UCONFIG_REG_END for performance countersNicolai Hähnle2015-11-252-2/+2
* radeon: add perfcounter-related EVENT_TYPEsNicolai Hähnle2015-11-251-0/+3
* radeon: additional constants for WAIT_REG_MEM and EVENT_WRITE_EOPNicolai Hähnle2015-11-251-0/+8
* nouveau: move interlaced assert down in nouveau_vp3_video_buffer_createJulien Isorce2015-11-251-1/+1
* softpipe/llvmpipe: don't advertize support for ASTCRoland Scheidegger2015-11-242-2/+4
* llvmpipe: don't test for unsupported formats in lp_test_formatRoland Scheidegger2015-11-241-0/+12
* radeon/llvm: Use llvm.AMDIL.exp intrinsic again for nowMichel Dänzer2015-11-241-1/+1
* radeon/uvd: uv pitch separation for stoneyBoyuan Zhang2015-11-232-1/+6
* svga: Add ASTC formats to format table.Jose Fonseca2015-11-231-0/+28
* freedreno/ir3: add support for a few gs5 opsIlia Mirkin2015-11-231-0/+27
* freedreno/a4xx: add ARB_texture_query_lod supportIlia Mirkin2015-11-232-6/+20
* freedreno/a4xx: re-emit program on dirty framebufferIlia Mirkin2015-11-231-1/+1
* freedreno/a4xx: use a factor of 32767 for snorm8 blendingIlia Mirkin2015-11-231-5/+34
* freedreno/a4xx: only compute texture offset once for the viewIlia Mirkin2015-11-233-13/+6
* freedreno/a4xx: add ARB_texture_view supportIlia Mirkin2015-11-233-8/+10
* freedreno/a4xx: add formats for ARB_texture_buffer_object_rgb32 supportIlia Mirkin2015-11-233-3/+9
* freedreno/a4xx: add ARB_texture_rgb10_a2ui supportIlia Mirkin2015-11-232-2/+3
* freedreno/a4xx: add astc formatsIlia Mirkin2015-11-232-1/+39
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