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* i915g: Don't write constants past I915_MAX_CONSTANTStéphane Marchesin2014-11-221-1/+1
| | | | | | | | This happens with glsl-convolution-1, where we have 64 constants. This doesn't make the test pass (we don't have 64 constants anyway, only 32) but this prevents it from crashing. Signed-off-by: Stéphane Marchesin <[email protected]>
* i915g: Don't hardcode array size for phase countStéphane Marchesin2014-11-221-1/+1
| | | | | | This is an array of temp registers, so use I915_MAX_TEMPORARY for the size. Signed-off-by: Stéphane Marchesin <[email protected]>
* radeonsi: use minnum and maxnum LLVM intrinsics for MIN and MAX opcodesMarek Olšák2014-11-211-0/+7
| | | | | | | So far it has been compiled into pretty ugly code (8 instructions or so for either opcode). Reviewed-by: Tom Stellard <[email protected]>
* vc4: Update for new kernel ABI with async execution and waits.Eric Anholt2014-11-209-3/+250
| | | | | Our submits now return immediately and you have to manually wait for things to complete if you want to (like a normal driver).
* radeonsi: remove unused variable si_state_dsa::db_render_controlMarek Olšák2014-11-191-1/+0
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* llvmpipe: enable PIPE_CAP_TGSI_VS_LAYER_VIEWPORTRoland Scheidegger2014-11-191-0/+1
| | | | | | | | | | | | No changes required in the driver itself, all handled by draw. piglit results in a quick run: skip->pass 7 skip->fail 2 (The new failures in the ARB_fragment_layer_viewport group are expected, we fail the same if gs doesn't write these outputs regardless of the vs.) Reviewed-by: Jose Fonseca <[email protected]>
* r600g: limit texture offset application to specific types (v2)Dave Airlie2014-11-191-3/+18
| | | | | | | | | | | | | | | | | | | | | | For 1D and 2D arrays we don't want the other coordinates being offset and affecting where we sample. I wrote this patch 6 months ago but lost it. Fixes: ./bin/tex-miplevel-selection textureLodOffset 1DArray ./bin/tex-miplevel-selection textureLodOffset 2DArray ./bin/tex-miplevel-selection textureOffset 1DArray ./bin/tex-miplevel-selection textureOffset 1DArrayShadow ./bin/tex-miplevel-selection textureOffset 2DArray ./bin/tex-miplevel-selection textureOffset(bias) 1DArray ./bin/tex-miplevel-selection textureOffset(bias) 2DArray v2: rewrite to handle more cases and be consistent with code above. Reviewed-by: Glenn Kennard <[email protected]> Cc: "10.3 10.4" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600g: geom shaders: always load texture src regs from inputsDave Airlie2014-11-191-1/+2
| | | | | | | | | | | Otherwise we seem to lose the split_gs_inputs and try and pull from an uninitialised register. fixes 9 texelFetch geom shader tests. Reviewed-by: Glenn Kennard <[email protected]> Cc: "10.3 10.4" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* vc4: Emit semaphore instructions for new kernel ABI.Eric Anholt2014-11-183-6/+87
| | | | | | | Previously, the kernel would dispatch thread 0, wait, then dispatch thread 1. By insisting that the thread contents use semaphores in the right place, the kernel can sleep for longer by dispatching both threads at once.
* vc4: Mark a big array as const.Eric Anholt2014-11-181-1/+1
| | | | Drops 1kb of code from this inner loop, in exchange for 2.5k of data.
* gallivm: fix alignment issue for vertex data fetchRoland Scheidegger2014-11-181-1/+2
| | | | | | | | | | | | | | We cannot guarantee that vertex buffers have the necessary alignment for fetching all AoS members at once (for instance 4x32bit XYZW data). We can however guarantee that for textures. This did not cause errors for older llvm versions but it now matters and will cause segfaults if the data happens to not be aligned. Thus we need to set alignment manually. (Note that we can't actually really guarantee data to be even element aligned due to offsets in vertex buffers being bytes and OpenGL allowing this, but it does not matter for x86 as alignment is only required for sse vectors - not sure what happens on other archs, however.) This fixes https://bugs.freedesktop.org/show_bug.cgi?id=85467.
* radeonsi: support gl_FragCoord at integer pixel centerMarek Olšák2014-11-182-1/+5
| | | | | | No known benefit for OpenGL, but it doesn't hurt. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: support per-sample gl_FragCoordMarek Olšák2014-11-181-12/+13
| | | | | Cc: 10.4 <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* r600g/cayman: handle empty vertex shadersDave Airlie2014-11-181-4/+8
| | | | | | | | | | | | | | Some of the geom shader tests produce an empty vertex shader, on cayman we'd crash in the finaliser because last_cf was NULL. cayman doesn't need the NOP workaround, so if the code arrives here with no last_cf, just emit an END. fixes crashes in a bunch of piglit geom shader tests. Cc: "10.3 10.4" <[email protected]> Reviewed-by: Glenn Kennard <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600g/cayman: fix texture gather testsDave Airlie2014-11-181-4/+11
| | | | | | | | | | It appears on cayman the TG4 outputs were reordered. This fixes a lot of piglit tests. Cc: "10.3 10.4" <[email protected]> Reviewed-by: Glenn Kennard <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600g: cayman umad assigns dst pointlesslyDave Airlie2014-11-181-1/+1
| | | | | | | | There is no need to assign dst here, just use the chan from j Pointed out by glennk. Signed-off-by: Dave Airlie <[email protected]>
* r600g/cayman: fix integer multiplication output overwrite (v2)Dave Airlie2014-11-181-3/+23
| | | | | | | | | | | This fixes tests/spec/glsl-1.10/execution/fs-op-assign-mult-ivec2-ivec2-overwrite.shader_test. hopeful fix for fd.o bug 85376 Reported-by: ghallberg Cc: "10.3 10.4" <[email protected]> Reviewed-by: Glenn Kennard <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radeonsi: Disable asynchronous DMA except for PIPE_BUFFERMichel Dänzer2014-11-171-0/+15
| | | | | | | | | | | | | | | | | Using the asynchronous DMA engine for multi-dimensional operations seems to cause random GPU lockups for various people. While the root cause for this might need to be fixed in the kernel, let's disable it for now. Before re-enabling this, please make sure you can hit all newly enabled paths in your testing, preferably with both piglit and real world apps, and get in touch with people on the bug reports below for stability testing. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=85647 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83500 Cc: "10.3 10.4" <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Grigori Goronzy <[email protected]>
* freedreno: add missing headers in Makefile.sourcesEmil Velikov2014-11-161-1/+14
| | | | | | ... or autotools will fail to pick them up for the distribution tarball. Signed-off-by: Emil Velikov <[email protected]>
* gallium: remove unused pipe_viewport_state::translate[3] and scale[3]Marek Olšák2014-11-163-5/+2
| | | | Almost all drivers ignore them.
* radeonsi: implement TGSI_PROPERTY_VS_WINDOW_SPACE_POSITIONMarek Olšák2014-11-163-3/+16
| | | | | | | Required by Nine. Reviewed-by: Michel Dänzer <[email protected]> Tested-by: Nick Sarnie <[email protected]>
* freedreno/a4xx: implement mem->gmem (restore)Rob Clark2014-11-152-3/+199
| | | | | | Support to restore gmem (tile buffer) (in case it wasn't glClear'd). Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: move where SP_FS_MRT_REGn is emittedRob Clark2014-11-152-14/+22
| | | | | | | Addition of color fmt bitfield to this register (compared to a3xx) means we need to re-emit if either prog or framebuffer state is dirty. Signed-off-by: Rob Clark <[email protected]>
* nv50,nvc0: use clip_halfz setting when creating rasterizer stateIlia Mirkin2014-11-156-3/+10
| | | | | | | This enables the ARB_clip_control extension. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.4" <[email protected]>
* freedreno: add adreno 420 supportRob Clark2014-11-1532-12/+3870
| | | | | | | | Very initial support. Basic stuff working (es2gears, es2tri, and maybe about half of glmark2). Expect broken stuff. Still missing: mem->gmem (restore), queries, mipmaps (blob segfaults!), hw binning, etc. Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2014-11-156-66/+2274
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: move some helpersRob Clark2014-11-142-65/+71
| | | | | | | Split out a few helpers from fd3_program so we don't have to duplicate for fd4_program. Signed-off-by: Rob Clark <[email protected]>
* freedreno: rename draw->draw_vboRob Clark2014-11-144-6/+6
| | | | | | | Gets rid of a namespace conflict w/ a4xx which wants an fd4_draw() version of fd_draw().. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: missing u_upload_destroyRob Clark2014-11-141-0/+2
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: fix borked check for a320.0Rob Clark2014-11-141-1/+1
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: half vs full reg in standalone compiler outputRob Clark2014-11-141-6/+10
| | | | | | Handle hrN.c in printing outputs/inputs. Signed-off-by: Rob Clark <[email protected]>
* llvmpipe: Call pipe_thread_wait() on Linux.José Fonseca2014-11-131-0/+6
| | | | | | | To address http://lists.freedesktop.org/archives/mesa-dev/2014-November/070569.html In short, revert 706ad3b649e6a75fdac9dc9acc3caa9e6067b853 for non-Windows OSes.
* i915g: we also have more than 0 viewports!Kenneth Graunke2014-11-121-0/+3
| | | | | | | | | See 546d6c8d for the corresponding fix in freedreno. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Stephane Marchesin <[email protected]> Cc: "10.3" <[email protected]>
* vc4: Avoid reusing a pointer from c->outputs[] after add_output().Eric Anholt2014-11-121-5/+6
| | | | add_output() can resize the qreg array, so we might use a stale pointer.
* vc4: Fix assumption of TGSI OUT[0] being POSITION in the VS.Eric Anholt2014-11-121-5/+5
| | | | | | | | All the shaders we've received so far had this be the case, but with nir-to-tgsi that changed. I might decide to make nir-to-tgsi keep the outputs in the same order, for debugging sanity, but I'm not sure.
* nvc0: remove unused mm_VRAM_fe0Ilia Mirkin2014-11-122-9/+0
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* ilo: clean up gen6_3DSTATE_SF()Chia-I Wu2014-11-113-90/+105
| | | | | | | | | | | Make the helpers fill out valid Gen7 3DSTATE_SF and 3STATE_SBE. This prevents the helpers from having to do dw[0] = GEN7_SBE_DW1_x; // setting DW1 value to dw[0]!? and simplifies gen7_3DSTATE_{SF,SBE}(). Signed-off-by: Chia-I Wu <[email protected]>
* ilo: clean up gen7_3DSTATE_STREAMOUT()Chia-I Wu2014-11-112-45/+35
| | | | | | | Render stream and render enable are independent from so enable. Having a single return point makes it easier to see that. Signed-off-by: Chia-I Wu <[email protected]>
* ilo: rework gen7_3DSTATE_SO_DECL_LIST()Chia-I Wu2014-11-111-60/+66
| | | | | | | Started to make pipe_stream_output_info mandatory, but ended up adding support for stream id and making a workaround Gen7-specific. Signed-off-by: Chia-I Wu <[email protected]>
* ilo: add 3DSTATE_SO_BUFFER variantsChia-I Wu2014-11-112-24/+25
| | | | | | Add gen7_disable_3DSTATE_SO_BUFFER() to disable SO buffers. Signed-off-by: Chia-I Wu <[email protected]>
* ilo: add gen6_3dstate_constant()Chia-I Wu2014-11-112-84/+67
| | | | | | | It replaces gen6_fill_3dstate_constant(). gen6_3DSTATE_CONSTANT_{VS,GS,PS} are made wrappers of the new function. Signed-off-by: Chia-I Wu <[email protected]>
* ilo: add variants of 3DSTATE_{HS,DS}Chia-I Wu2014-11-112-12/+6
| | | | | | Rename them to gen7_disable_3DSTATE_{HS,DS}() to reflect the fact. Signed-off-by: Chia-I Wu <[email protected]>
* ilo: add variants of 3DSTATE_GSChia-I Wu2014-11-113-63/+100
| | | | | | | Add gen6_so_3DSTATE_GS(), gen6_disable_3DSTATE_GS(), and gen7_disable_3DSTATE_GS() to do SO on GEN6 or to disable GS. Signed-off-by: Chia-I Wu <[email protected]>
* ilo: add variants of 3DSTATE_VSChia-I Wu2014-11-113-16/+22
| | | | | | Add gen6_disable_3DSTATE_VS() to disable VS. Signed-off-by: Chia-I Wu <[email protected]>
* ilo: add variants of 3DSTATE_PSChia-I Wu2014-11-112-36/+41
| | | | | | Add gen7_disable_3DSTATE_PS() to disable PS. Signed-off-by: Chia-I Wu <[email protected]>
* ilo: add variants of 3DSTATE_WMChia-I Wu2014-11-113-54/+61
| | | | | | | Add gen6_hiz_3DSTATE_WM() and gen7_hiz_3DSTATE_WM() for HiZ ops without dispatching. Signed-off-by: Chia-I Wu <[email protected]>
* ilo: add variants of 3DSTATE_CLIPChia-I Wu2014-11-113-24/+32
| | | | | | Add gen6_disable_3DSTATE_CLIP to disable clipping. Signed-off-by: Chia-I Wu <[email protected]>
* ilo: prefix 3DSTATE_VF with gen75Chia-I Wu2014-11-112-4/+4
| | | | | | 3DSTATE_VF is Gen7.5+ only. Signed-off-by: Chia-I Wu <[email protected]>
* ilo: derive fb blending caps at bind timeChia-I Wu2014-11-103-78/+101
| | | | | | | | Derive whether a RT supports blending, logicop, and the like when set_framebuffer_state() is called. This enables us to simplify gen6_BLEND_STATE(). Signed-off-by: Chia-I Wu <[email protected]>
* ilo: remove inlined state functionsChia-I Wu2014-11-104-236/+177
| | | | | | | We had some inlined state functions for dispatching. They were not needed with the new top/bottom split. Signed-off-by: Chia-I Wu <[email protected]>
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