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* broadcom/vc5: Disable early Z test when the FS writes Z.Eric Anholt2017-11-071-1/+2
* broadcom/vc5: Shift the min/max lod fields by the BASE_LEVEL.Eric Anholt2017-11-072-4/+15
* broadcom/vc5: Add support for anisotropic filtering.Eric Anholt2017-11-071-0/+9
* broadcom/vc5: Fix mipmap filtering enums.Eric Anholt2017-11-071-6/+8
* broadcom/vc5: Fix height padding of small UIF slices.Eric Anholt2017-11-071-1/+5
* broadcom/vc5: Print the actual offsets in HW for our resource layout debug.Eric Anholt2017-11-071-34/+55
* broadcom/vc5: Set the available VS outputs to match the FS inputs.Eric Anholt2017-11-071-1/+4
* broadcom/vc5: Set the max texture LOD bias.Eric Anholt2017-11-071-1/+1
* broadcom/vc5: Fix translation of stencil ops.Eric Anholt2017-11-072-8/+30
* broadcom/vc5: Move stencil state packing to the CSO.Eric Anholt2017-11-073-27/+47
* broadcom/vc5: Introduce a helper for pre-packing our V3DXX structs.Eric Anholt2017-11-072-165/+155
* broadcom/vc5: Add a cl_emit() variant for merging with a pre-packed struct.Eric Anholt2017-11-072-19/+29
* broadcom/vc5: Skip emitting depth offset while disabled.Eric Anholt2017-11-071-1/+4
* broadcom/vc5: Don't emit stencil config if not doing stencil test.Eric Anholt2017-11-071-1/+2
* broadcom/vc5: Don't emit updated blend factors/funcs while disabled.Eric Anholt2017-11-071-1/+5
* broadcom/vc5: Make sure the TMU indirect struct is appropriately aligned.Eric Anholt2017-11-071-0/+2
* broadcom/vc5: Use DEPTH24_STENCIL8 for rendering to depth-only textures.Eric Anholt2017-11-071-1/+1
* radeonsi: add si_screen::has_ls_vgpr_init_bugMarek Olšák2017-11-074-3/+5
* radeonsi: use ac_create_target_machineMarek Olšák2017-11-071-15/+7
* radeonsi: use ac_get_llvm_processor_nameMarek Olšák2017-11-073-38/+4
* radeonsi/gfx9: don't set gs_table_depthMarek Olšák2017-11-071-2/+4
* radeonsi/gfx9: limit the scissor bug workaround to Vega10 and Raven onlyMarek Olšák2017-11-071-4/+4
* etnaviv: Don't over-pad compressed texturesWladimir J. van der Laan2017-11-061-9/+15
* etnaviv: ASTC texture supportWladimir J. van der Laan2017-11-067-2/+57
* etnaviv: Update from rnndbWladimir J. van der Laan2017-11-0613-320/+1015
* radeonsi: enable signed vertex buffer offsetsMarek Olšák2017-11-062-15/+12
* gallium: add PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSETMarek Olšák2017-11-0616-0/+16
* radeonsi: don't map big VRAM buffers for the first upload directlyMarek Olšák2017-11-062-0/+21
* gallium/u_threaded: don't map big VRAM buffers for the first upload directlyMarek Olšák2017-11-061-2/+8
* nv50,nvc0: Display shared memory usage in pipe_debug_messagePierre Moreau2017-11-042-6/+8
* nv50,nvc0: Copy shared memory per block to the program info structure and backPierre Moreau2017-11-042-0/+4
* nv50/ir: Store shared memory per block in nv50_ir_prog_infoPierre Moreau2017-11-041-0/+1
* winsys/amdgpu: Add R600_DEBUG flag to reserve VMID per ctx.Andrey Grodzovsky2017-11-032-0/+2
* i915g: remove some unknown cap warnings.Dave Airlie2017-11-031-0/+8
* i915g: make gears run again.Dave Airlie2017-11-034-4/+24
* ac/radeonsi: add support for tex instr without a derefenceTimothy Arceri2017-11-031-0/+5
* r600: add support for early depth/stencil.Dave Airlie2017-11-031-0/+3
* r600: add support for emitting RAT instructions to the assembler.Dave Airlie2017-11-033-0/+35
* r600: add support for mark bit to the assembler.Dave Airlie2017-11-033-0/+7
* r600: add support for valid pixel mode on CF clausesDave Airlie2017-11-032-0/+2
* r600: add support for some ALU sources.Dave Airlie2017-11-031-0/+9
* radeonsi: remove 'Authors:' commentsMarek Olšák2017-11-0235-140/+0
* etnaviv: Allow clearing constant buffer using buffer==NULL user_buffer==NULLWladimir J. van der Laan2017-11-021-1/+1
* etnaviv: Don't flush on transfer when UNSYNCHRONIZEDWladimir J. van der Laan2017-11-021-12/+12
* etnaviv: don't do resolve-in-place without valid TSWladimir J. van der Laan2017-11-024-0/+11
* svga: Use __asm__ instead of asmDylan Baker2017-11-012-8/+5
* Revert "winsys/amdgpu: Add R600_DEBUG flag to reserve VMID per ctx."Marek Olšák2017-11-012-2/+0
* gallium: add cap for driver specified max combined shader resources.Dave Airlie2017-11-0116-0/+16
* r600/sb: bail out if prepare_alu_group() doesn't find a proper schedulingGert Wollny2017-11-012-20/+31
* radeonsi: fix culldist_writemask in nir pathTimothy Arceri2017-11-011-2/+1
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