summaryrefslogtreecommitdiffstats
path: root/src/gallium/drivers
Commit message (Collapse)AuthorAgeFilesLines
* radeonsi: emit dirty consecutive pointers in one SET_SH_REG packetMarek Olšák2017-10-171-27/+39
| | | | | | IB size: -1.6% Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: split si_emit_shader_pointerMarek Olšák2017-10-171-11/+23
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: generalize the SI_VS_SHADER_POINTER_MASK macroMarek Olšák2017-10-173-4/+4
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: use SPI_SHADER_USER_DATA_COMMONMarek Olšák2017-10-171-13/+13
| | | | | | IB size: -0.4% Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: move RW_BUFFERS from s[0:1] to s[8:9] for HS and GSMarek Olšák2017-10-172-39/+16
| | | | | | | Let's use the same user data SGPRs in all stages. (for SPI_SHADER_USER_DATA_COMMON_0) Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: add GFX-IB-size query to the HUDMarek Olšák2017-10-173-0/+6
| | | | | | It shows the sum of all IBs per frame. Reviewed-by: Nicolai Hähnle <[email protected]>
* broadcom/vc4: Fix false-positive for the tiling ioctls on simulator mode.Eric Anholt2017-10-171-0/+1
| | | | | If there happened to be an ENOENT laying around, we would try using the ioctls later and fail out resource allocation.
* broadcom/vc4: Skip BO labeling when in simulator mode.Eric Anholt2017-10-172-1/+5
| | | | | It was calling down into i915 trying to label the BO, which is definitely not the right thing.
* broadcom/vc5: Don't forget to set the RT format for 1555 textures.Eric Anholt2017-10-171-2/+2
| | | | Fixes dEQP-GLES3.functional.fbo.completeness.renderable.texture.color0.rgb5_a1
* meson: build llvmpipeDylan Baker2017-10-161-0/+116
| | | | | Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* meson: build softpipeDylan Baker2017-10-161-0/+85
| | | | | | | | | | This doesn't include llvmpipe. v2: - Fix inconsistent use of with_gallium_swrast and with_gallium_softpipe. Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* meson: build nouveau (gallium) driverDylan Baker2017-10-161-0/+224
| | | | | | | | | | | Tested with a GK107. v2: - Add target for nouveau standalone compiler. This target is not built by default. v3: - Add nouveau to list of drivers built by default Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Anholt <eric at anholt.net>
* meson: build radeonsi gallium driverDylan Baker2017-10-161-1/+1
| | | | | | | | | | This hooks up the bits necessary to build gallium dri drivers, with radeonSI as the first example driver. This isn't tested yet. v4: - drop radeonsi generated header from sources. Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Anholt <eric at anholt.net>
* meson: build radeonsiDylan Baker2017-10-162-0/+133
| | | | | | | | This builds the radeonsi (and radeon) window system bits and gallium driver bits. Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Anholt <eric at anholt.net>
* meson: build gallium helper driversDylan Baker2017-10-164-0/+112
| | | | | | | This builds ddebug, noop, rbug, and trace drivers. Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Anholt <eric at anholt.net>
* svga: format the version string like the rest of mesaEric Engestrom2017-10-161-5/+5
| | | | | | | | All 4 other version strings do it like this. ((Also, double parentheses just look confusing)) Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* svga: fix format_conversion_table breakageBrian Paul2017-10-161-2/+7
| | | | | | | | | | The new A1B5G5R5_UNORM, X1B5G5R5_UNORM formats were added in the wrong place in commit ef874ee450b18e. Fixes: ef874ee450b18e "gallium: Add support for 5551 with the 1-bit field in the low bit." Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* a2xx: add support for a few 16-bit color rendering formatsIlia Mirkin2017-10-152-1/+11
| | | | | | | | The rest should be possible too, just needs some additional investigation. Passes fbo-*-formats piglit tests. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Wladimir J. van der Laan <[email protected]>
* freedreno/a20x: Enable rendering to RGBA/RGBXWladimir J. van der Laan2017-10-151-1/+3
| | | | | Signed-off-by: Wladimir J. van der Laan <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* freedreno/a20x: Fix rendering to BGRXWladimir J. van der Laan2017-10-151-0/+1
| | | | | | | Make sure that BGRX rendering is swapped the correct way around. Signed-off-by: Wladimir J. van der Laan <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* etnaviv: rework TS enable to be a derived stateLucas Stach2017-10-143-5/+43
| | | | | | | | | | | | | | | Draw operations should not use the TS if the TS buffer content is invalid, as this leads to wrong rendering or even GPU hangs. As the TS valid status can change between draws (clear operations changing it to valid, blits using the RS to the color or ZS buffer changing it to invalid), the TS_MEM_CONFIG must be updated before each draw if the status has changed. This fixes the remaining TS related piglit failures (regressions of a standard run against a piglit run with TS completely disabled). Signed-off-by: Lucas Stach <[email protected]> Reviewed-by: Wladimir J. van der Laan <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: skip unused vertex attributes when assigning VS inputsLucas Stach2017-10-141-0/+4
| | | | | | | | | | | | | When not all of the vertex attributes are actually used in the shader, we end up with some inputs without an assigned reg. Those are marked as invalid and must be skipped when assigning the inputs, as those would overwrite other valid inputs otherwise. Fixes piglit drawpixels and a bunch of other tests using the st_draw path. Signed-off-by: Lucas Stach <[email protected]> Reviewed-by: Wladimir J. van der Laan <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* broadcom/vc5: Remove the u_resource_vtbl usage.Eric Anholt2017-10-123-25/+18
| | | | Like for vc4, this was just a wasted indirection.
* radeonsi: implement sync_file import/exportMarek Olšák2017-10-122-2/+79
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: implement sync_file import/exportMarek Olšák2017-10-121-0/+12
| | | | | | syncobj is used internally for interactions with command submission. Reviewed-by: Nicolai Hähnle <[email protected]>
* ac: add radeon_info::has_sync_filecros-mesa-17.2.3-vanillachadv/cros-mesa-17.2.3-vanillaMarek Olšák2017-10-121-0/+1
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium: add pipe_screen::check_resource_capabilityMarek Olšák2017-10-124-0/+57
| | | | | | | | | This is optional (and no CAP). Implemented by radeonsi, ddebug, rbug, trace. Reviewed-by: Daniel Stone <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* etnaviv: Do GC3000 resolve-in-place when possibleWladimir J. van der Laan2017-10-124-4/+25
| | | | | | | | | | | | | If an RS blit is done with source exactly the same as destination, and the hardware supports this, do an in-place resolve. This only fills in tiles that have not been rendered to using information from the TS. This is the same as the blob does and potentially saves significant bandwidth when doing i.MX6qp scanout using PRE, and when rendering to textures (though here using sampler TS would be even better). Signed-off-by: Wladimir J. van der Laan <[email protected]> Reviewed-by: Lucas Stach <[email protected]>
* radeonsi: add support for PIPE_FORMAT_{X1,A1}R5G5B5_UNORMNicolai Hähnle2017-10-121-0/+8
| | | | | | Fixes dEQP-EGL.functional.image.modify.tex_rgb5_a1_tex_subimage_rgba8 Reviewed-by: Marek Olšák <[email protected]>
* swr: simd16 shaders work in progressTim Rowley2017-10-113-2/+21
| | | | | | | | Start building vertex shaders as simd16. Disabled by default, set USE_SIMD16_SHADERS in knobs.h to experiment. Reviewed-by: Bruce Cherniak <[email protected]>
* nv50,nvc0: fix push hint logic in presence of a start offsetIlia Mirkin2017-10-112-7/+5
| | | | | | | | | | | | | | | | Previously buffer offsets were passed in explicitly as an offset, which had to be added to the resource address. Now they are passed in via an increased 'start' parameter. As a result, we were double-adding the start offset in this kind of situation. This condition was triggered by piglit's draw-elements test which has a requisite glMultiDrawElements in combination with a small enough number of vertices to go through the immediate push path. Fixes: 330d0607ed6 ("gallium: remove pipe_index_buffer and set_index_buffer") Reported-by: Karol Herbst <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Cc: [email protected]
* Android: fix build break from r600/radeon splitRob Herring2017-10-102-1/+5
| | | | | | | | | | | | | | | Commit 06bfb2d28f7a ("r600: fork and import gallium/radeon") broke the Android build: external/mesa3d/src/gallium/drivers/radeon/r600_pipe_common.c:43:10: fatal error: 'llvm-c/TargetMachine.h' file not found ^~~~~~~~~~~~~~~~~~~~~~~~ Update the Android makefiles so that drivers/radeon is only built when radeonsi (and therefore LLVM) is enabled. Fixes: 06bfb2d28f7a (r600: fork and import gallium/radeon) Acked-by: Marek Olšák <[email protected]> Signed-off-by: Rob Herring <[email protected]>
* r600: cleanup llvm ir target selection.Dave Airlie2017-10-111-18/+2
| | | | | | | Only r600 target used now for compute IR. Reviewed-by: Nicolai Hähnle <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: drop tc_L2_dirty bit, this was SI only.Dave Airlie2017-10-113-15/+0
| | | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radeonsi: lower ffma in nir to mad.Dave Airlie2017-10-111-0/+1
| | | | | | | | | | | This lowers ffma to a * b + c. This seems like it should keep Marek happiest, so we'd never get to the fma instruction emission code. Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* broadcom/vc5: Fix handling of 5551 textures using the new gallium format.Eric Anholt2017-10-101-2/+2
| | | | | Like vc4, we have the alpha in the low bit. Fixes a bunch of piglit texwrap failures.
* broadcom/vc5: Set the RCL's MSAA mode to match the BCL's MSAA state.Eric Anholt2017-10-101-0/+2
|
* braodcom/vc5: Set up clear color for higher-bpp formats.Eric Anholt2017-10-101-4/+25
| | | | Fixes arb_color_buffer_float-clear
* broadcom/vc5: Set up per-MRT clear colors.Eric Anholt2017-10-103-41/+22
| | | | Fixes fbo-mrt-alphatest.
* broadcom/vc5: Fix blendfactor zero handling.Eric Anholt2017-10-101-0/+1
| | | | | I cut the line out to move it up to the top, when putting "0" in the switch made the compiler complain that that wasn't a valid enum.
* broadcom/vc5: Add support for f32 render targets.Eric Anholt2017-10-101-0/+4
| | | | | The TLB write code is getting ugly and needs a refactoring (that will hopefully handle TLBU uniform coalescing as well).
* broadcom/vc5: Fix color masks for non-independent blending.Eric Anholt2017-10-101-8/+16
| | | | This gets fbo-mrt-alphatest working except for the second RT's clear color.
* broadcom/vc5: Make the BCL's number of render targets setup match the RCL.Eric Anholt2017-10-101-1/+2
|
* braodcom/vc5: Fix tile size setup for MRTs.Eric Anholt2017-10-101-2/+2
| | | | | We need to divide the TLB in two for the 2nd color buffer, and again if the 3rd or 4th are present.
* broadcom/vc5: Start hooking up multiple render targets support.Eric Anholt2017-10-101-3/+9
| | | | We now emit as many TLB color writes as there are color buffers.
* broadcom/vc5: Add support for GL_EXT_provoking_vertex.Eric Anholt2017-10-102-1/+4
| | | | | The bit was missing from the spec, but it's there in the simulator. Fixes the piglit clipflat test.
* braodcom/vc5: Find the actual first TF output for our TF spec.Eric Anholt2017-10-101-1/+6
| | | | This doesn't yet support PSIZ, but gets us at least some of TF working.
* broadcom/vc5: Fix translation of transform feedback's output_register field.Eric Anholt2017-10-101-2/+16
| | | | It's a NIR driver_location, not a slot offset.
* broadcom/vc5: Mark our primitives as needing TF processing.Eric Anholt2017-10-101-4/+11
| | | | | The TF enable state appears to stick around until the next TF enable packet is sent, so we only want to request TF when the shader is using it.
* broadcom/vc5: Fix setup of TF dword output count.Eric Anholt2017-10-101-1/+1
| | | | I missed the "- 1" when reading the spec.
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-29 02:49:39 +0000