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* freedreno/ir3: drop unused create_input() argRob Clark2015-07-271-11/+8
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: move emit_const to ir3Rob Clark2015-07-2712-229/+263
| | | | | | | | | | | | | | | Details of the cmdstream packets are different between a3xx and a4xx, but the logic about the layout of const registers is the same, as that is dictated by the ir3 shader compiler. So rather than duplicating logic that is tightly coupled to ir3 between a3xx and a4xx, move this into ir3 and use per-generation callbacks for to build the cmdstream packets. This should make it easier to pass additional const regs (such as for transform feedback). And it also keeps the layout internal to ir3 in case we want to make the layout more dynamic some day. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: bit of shader API refactoringRob Clark2015-07-277-22/+25
| | | | | | | | | | | | Since for transform-feedback, we'll need more than just the TGSI tokens from the state object, just pass the entire state object to ir3_shader_create(). This also cleans things up a bit for some day in the future when we could take shader either as TGSI or directly NIR (for ex, glsl2nir or spirv2nir paths). In the same spirit, drop extra args from ir3_compile_shader_nir() (since it can anyways get what it needs from the ir3_shader_variant). Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: updated cat6 encodingRob Clark2015-07-275-113/+230
| | | | | | | Sync updated cat6 encoding from freedreno.git, needed to properly encode store instructions. Signed-off-by: Rob Clark <[email protected]>
* radeonsi: add fine derivate control (v2.1)Dave Airlie2015-07-252-6/+48
| | | | | | | | | | | | | This adds support for fine derivatives and enables ARB_derivative_control on radeonsi. (just fell out of my working out interpolation) v2: cleanup some bits, write a comment v2.1: take Michel's comment from the mailing list Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radeonsi: fix GLSL textureGrad(samplerCube*) functionsMarek Olšák2015-07-253-34/+90
| | | | | | +4 piglits Reviewed-by: Michel Dänzer <[email protected]>
* nvc0: fix geometry program revalidation of clipping paramsIlia Mirkin2015-07-251-1/+1
| | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Cc: [email protected]
* radeonsi: ubo indexing support (v2)Dave Airlie2015-07-251-3/+12
| | | | | | | | | | | | This is required as part of ARB_gpu_shader5. no backend changes are required for this, or if any are, it's the same ones as for samplers. v2: use get_indirect_index (Marek) Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radeonsi: add support for indirect samplers (v2)Dave Airlie2015-07-251-8/+41
| | | | | | | | | | | | This adds the frontend support, however the llvm backend produces the wrong pattern, however we can conditionalise enabling ARB_gpu_shader5 on whatever version of llvm we fix this in. v2: drop unneeded sampler_indirect checks (Marek) Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radeonsi: split out interpolation input selectionDave Airlie2015-07-252-26/+38
| | | | | | | | | | | This is prep work for using it in the interpolation code later. Also add storage for the input interpolation mode so we can pick it up later. Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radeonsi: separate out load sample positionDave Airlie2015-07-251-18/+26
| | | | | | | | This is prep work for reusing this in the interpolation code later. Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* nvc0/ir: per-patch vars are in a separate address spaceIlia Mirkin2015-07-242-11/+9
| | | | | | | | | | | | | There's no need to attempt to avoid overlapping generic i/o with patch i/o. By the same token, we can't merge patch and non-patch loads/stores. This fixes at least the tes-both-input-array-*-index-rd tessellation variable-indexing tests. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: kepler can't do indirect shader input/output loads directlyIlia Mirkin2015-07-238-6/+75
| | | | | | | | | | | | | | There's a special AL2P instruction (called AFETCH in nv50 ir) which computes a "physical" value to be used with indirect addressing with ALD. Fixes tcs-input-array-*-index-rd tcs-output-array-*-index-wr varying-indexing tessellation tests on Kepler. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: tess factors are now sysvals, adapt codegen to expect thatIlia Mirkin2015-07-236-11/+24
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* gk110/ir: fake BAR supportIlia Mirkin2015-07-231-0/+12
| | | | | | Makes things sorta work until we figure out the real way to do this. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: cleanup private enums that have graduated to galliumIlia Mirkin2015-07-232-7/+0
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: allow tess eval output loads to be CSE'dIlia Mirkin2015-07-231-0/+2
| | | | | | These only happen for gl_TessCoord which are constant. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: add hazard for 2nd dim of vfetch/load indirect argumentIlia Mirkin2015-07-231-0/+2
| | | | | | | Apparently a multi-word load can potentially overwrite the indirect sources, so make sure that RA picks different registers for those. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: patch vertex count is stored in the upper bitsIlia Mirkin2015-07-231-0/+4
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* nvc0/ir: add support for reading outputs in tess control shadersIlia Mirkin2015-07-232-2/+18
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: set perPatch flag on load/stores to per-patch varyingsIlia Mirkin2015-07-231-2/+6
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: populate info structure based on new tess propertiesIlia Mirkin2015-07-231-0/+18
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: mark varyings as per-patch based on semantic nameIlia Mirkin2015-07-232-4/+16
| | | | | | Also add proper handling for PATCH semantics Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: TESSCOORD comes in as a sysval, not an inputIlia Mirkin2015-07-232-11/+10
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: add handling for set_tess_state callbackIlia Mirkin2015-07-233-0/+34
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: add support for setting patch vertices at draw timeIlia Mirkin2015-07-234-3/+8
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: support MAX_SHADER_PATCH_VARYINGSIlia Mirkin2015-07-231-1/+2
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* nvc0: preliminary tess supportIlia Mirkin2015-07-2310-54/+86
| | | | | | | Uncomment the various functionality that was already there and add in obvious missing bits that parallel vp/gp/fp functionality. Signed-off-by: Ilia Mirkin <[email protected]>
* radeonsi: enable tessellation, update GL3.txt & release notesMarek Olšák2015-07-231-3/+11
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: add scratch buffer support for tessellation shadersMarek Olšák2015-07-231-8/+28
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: update invariant registers for tessellationMarek Olšák2015-07-231-2/+6
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: add assertions into draw_vbo and check tessellationMarek Olšák2015-07-231-1/+7
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: set the rasterization primitive type for tessellationMarek Olšák2015-07-231-0/+3
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: set VGT_LS_HS_CONFIG for tessellationMarek Olšák2015-07-233-4/+28
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: update IA_MULTI_VGT_PARAM for tessellationMarek Olšák2015-07-231-3/+51
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: add derived tessellation stateMarek Olšák2015-07-234-3/+146
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: implement a fixed-function tessellation control shader and its stateMarek Olšák2015-07-234-1/+68
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: set up a ring buffer for tessellation factorsMarek Olšák2015-07-234-0/+42
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: add tessellation shader statesMarek Olšák2015-07-233-13/+203
| | | | | | ls_rsrc# will be emitted as part of the derived tessellation state Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: update si_get_vs_info and si_get_vs_state for tessellationMarek Olšák2015-07-231-2/+8
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: add shader code generation for tessellationMarek Olšák2015-07-235-29/+851
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: implement TGSI_OPCODE_BARRIERMarek Olšák2015-07-231-0/+12
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: program VGT_SHADER_STAGES_EN for tessellationMarek Olšák2015-07-234-23/+45
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: add translation of PATCH primitivesMarek Olšák2015-07-231-0/+2
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: add support for tessellation shader resources and samplersMarek Olšák2015-07-232-8/+37
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: add code for creating, binding and destroying tessellation shadersMarek Olšák2015-07-233-0/+74
| | | | | | This doesn't do anything yet. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: add debug flags for dumping tessellation shadersMarek Olšák2015-07-232-9/+17
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: rework how shader pointers to descriptors are setMarek Olšák2015-07-235-91/+156
| | | | | | | | | | | | | | | | | This is mainly needed for tessellation where a VS can be bound as VS, ES, or LS, and TES (tess. evaluationshader) can be bound as VS or ES or neither. Therefore we need the ability to move pointers to descriptors between shaders arbitrarily. The idea is that the context has a mapping from PIPE_SHADER_x to SPI_SHADER_USER_DATA_x. After a shader is enabled or disabled, si_shader_change_notify should be called to update this mapping accordingly. There is a dirty flag for each shader pointer, but only one emit function for all pointers in the whole context, whose code and logic is separated from descriptors. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: rename build_streamout_store -> build_tbuffer_store_dwordsMarek Olšák2015-07-231-12/+12
| | | | | | It will be reused later. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: separate primitive ID computationMarek Olšák2015-07-231-7/+20
| | | | | | Support for new shader stages will be added here. Reviewed-by: Michel Dänzer <[email protected]>
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