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* radeonsi: decrease the number of compiler threads to num CPUs - 1Marek Olšák2017-06-071-1/+4
* radeonsi: drop unfinished shader compilations when destroying shadersMarek Olšák2017-06-072-3/+5
* freedreno/a5xx: set SP_BLEND_CONTROL properlyRob Clark2017-06-073-1/+4
* freedreno/a5xx: LRZ supportRob Clark2017-06-0714-14/+234
* freedreno: drop timestamp fieldRob Clark2017-06-072-3/+0
* freedreno/a5xx: refactor out helper for LRZ flushRob Clark2017-06-073-11/+19
* freedreno: reshuffle FD_MESA_DEBUG bitmaskRob Clark2017-06-071-3/+3
* freedreno: update generated headersRob Clark2017-06-077-17/+31
* gallium/u_blitter: use 2D_ARRAY for cubemap blits if possibleMarek Olšák2017-06-073-3/+3
* tree-wide: remove trailing backslashEric Engestrom2017-06-073-4/+4
* radeonsi: fix a GPU hang with tessellation on 2-CU configsMarek Olšák2017-06-061-1/+5
* radeon: remove out of date LLVM_REVISION.txtEmil Velikov2017-06-052-4/+0
* r600: refactor out some compressed resource state code.Dave Airlie2017-06-061-24/+28
* r600: document some of the missing shader constants.Dave Airlie2017-06-061-0/+4
* r600: add register info for atomic counters.Dave Airlie2017-06-062-0/+51
* r600: add missing RAT registers and operations.Dave Airlie2017-06-063-0/+59
* r600/sb: fix typo in field definitionsDave Airlie2017-06-061-1/+1
* r600: fix incorrect and missing bit field in register headers.Dave Airlie2017-06-051-3/+4
* nvc0: Add support for ARB_post_depth_coverageLyude2017-06-028-1/+15
* gallium: Add a cap to check if the driver supports ARB_post_depth_coverageLyude2017-06-0215-0/+15
* nvc0: disable BGRA8 images on FermiLyude2017-06-021-5/+14
* etnaviv: always do cpu_fini in transfer_unmapLucas Stach2017-06-011-3/+6
* nvc0: Clean up unnecessary includes from gallium/auxiliary/vl/Rhys Kidd2017-06-011-3/+0
* r600/eg: add support for tracing IBs after a hang.Dave Airlie2017-06-0111-7/+785
* radeonsi: remove unused si_pm4_state::compute_pktSamuel Pitoiset2017-05-312-4/+1
* radeonsi: remove chip_class define from si_pm4.hSamuel Pitoiset2017-05-311-1/+0
* radeonsi: merge si_pm4_free_state_simple() into si_pm4_free_state()Samuel Pitoiset2017-05-312-8/+2
* freedreno/a5xx: drop WFIs in emit_marker5()Rob Clark2017-05-301-5/+0
* freedreno/a5xx: timestamp / time-elapsed queriesRob Clark2017-05-302-1/+97
* freedreno/a5xx: rename query result structRob Clark2017-05-301-23/+22
* freedreno: update generated headersRob Clark2017-05-306-18/+624
* swr/rast: code cleanup (no functional change)Tim Rowley2017-05-301-2/+6
* swr/rast: whitespace changesTim Rowley2017-05-303-8/+3
* swr/rast: code cleanup (no functional change)Tim Rowley2017-05-301-3/+4
* swr/rast: allow early-z if shader uses depth valueTim Rowley2017-05-301-1/+1
* swr/rast: move wireframe/point triangle binning after cullingTim Rowley2017-05-301-80/+76
* swr/rast: remove unused functionsTim Rowley2017-05-301-28/+0
* swr/rast: code cleanup (no functional change)Tim Rowley2017-05-301-60/+64
* swr/rast: move binner utility functions to binner.hTim Rowley2017-05-303-193/+225
* swr/rast: SIMD16 FE - fix/use SIMD16 calcDeterminantIntVertical()Tim Rowley2017-05-303-43/+65
* swr/rast: add renderTargetArrayIndex to SWR_PS_CONTEXTTim Rowley2017-05-302-5/+6
* swr/rast: make simd16 logicops avx512f safeTim Rowley2017-05-301-4/+10
* swr/rast: SIMD16 FE - add SIMD16 types to jitterTim Rowley2017-05-303-10/+11
* swr/rast: SIMD16 FE - fix PA_STATE_OP::Reset()Tim Rowley2017-05-301-0/+3
* swr/rast: SIMD16 FE - simplify/refactor StreamOutTim Rowley2017-05-301-42/+0
* swr/rast: SIMD16 FE - fix conservative rasterizationTim Rowley2017-05-301-0/+32
* swr/rast: SIMD16 FE - interleaved simdvertex output in GSTim Rowley2017-05-302-20/+31
* swr/rast: fix _simd16_movemask_(ps,pd) native AVX512 intrinsicsTim Rowley2017-05-301-4/+4
* swr/rast: SIMD16 FE - primitive assembly simplificationTim Rowley2017-05-302-50/+32
* swr/rast: silence write of cfg graphTim Rowley2017-05-301-3/+3
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