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* virgl: make transfer code with PIPE_BUFFER targetsGurchetan Singh2018-12-191-2/+4
| | | | | | | util_format_get_blocksize returns 1 for R8 formats (all PIPE_BUFFERs are R8). Reviewed-by: Elie Tournier <[email protected]>
* virgl: consolidate transfer codeGurchetan Singh2018-12-195-59/+73
| | | | | | | | We could allocate and destroy transfers in one place. v2: Keep l_stride around. Reviewed-by: Elie Tournier <[email protected]>
* virgl: store layer_stride in metadataGurchetan Singh2018-12-192-6/+6
| | | | Reviewed-by: Elie Tournier <[email protected]>
* virgl: move vrend_get_tex_image_offset to common codeGurchetan Singh2018-12-193-26/+28
| | | | | | Will be reused. Reviewed-by: Elie Tournier <[email protected]>
* virgl: move virgl_resource_layout to common codeGurchetan Singh2018-12-193-42/+51
| | | | | | Will be reused. Reviewed-by: Elie Tournier <[email protected]>
* virgl: move texture metadata to common codeGurchetan Singh2018-12-192-12/+18
| | | | | | Will be reused. Reviewed-by: Elie Tournier <[email protected]>
* virgl: remove unnessecary codeGurchetan Singh2018-12-191-3/+0
| | | | | | | | | With commit 89b479, we moved to tracking buffer cleanliness when binding. TEST=dEQP-GLES31.functional.image_load_store.buffer.load_store.r32ui Reviewed-by: Elie Tournier <[email protected]>
* virgl: texture_transfer_pool --> transfer_poolGurchetan Singh2018-12-196-11/+11
| | | | | | It's used for all types of resources. Reviewed-by: Elie Tournier <[email protected]>
* radeonsi: const-ify the si_query_opsNicolai Hähnle2018-12-193-5/+5
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: split perfcounter queries from si_query_hwNicolai Hähnle2018-12-191-50/+93
| | | | | | | Remove a level of indirection to make the code more explicit -- should make it easier to follow what's going on. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: factor si_query_buffer logic out of si_query_hwNicolai Hähnle2018-12-194-110/+99
| | | | | | | | | | | This is a move towards using composition instead of inheritance for different query types. This change weakens out-of-memory error reporting somewhat, though this should be acceptable since we didn't consistently report such errors in the first place. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: move query suspend logic into the top-level si_query structNicolai Hähnle2018-12-193-44/+62
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: move remaining perfcounter code into si_perfcounter.cNicolai Hähnle2018-12-197-766/+643
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: track constant buffer bind history in si_pipe_set_constant_bufferNicolai Hähnle2018-12-191-2/+3
| | | | | | Other callers of si_set_constant_buffer don't need it. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: use si_set_rw_shader_buffer for setting streamout buffersNicolai Hähnle2018-12-191-50/+11
| | | | | | Reduce the number of places that encode buffer descriptors. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: add an si_set_rw_shader_buffer convenience functionNicolai Hähnle2018-12-192-45/+64
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: avoid using hard-coded SI_NUM_RW_BUFFERSNicolai Hähnle2018-12-191-1/+2
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: show the fixed function TCS in debug dumpsNicolai Hähnle2018-12-191-2/+8
| | | | | | This is rather important for merged VS/TCS as LSHS shaders... Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: const-ify si_set_tesseval_regsNicolai Hähnle2018-12-191-2/+2
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: rename SI_RESOURCE_FLAG_FORCE_TILING to clarify its purposeNicolai Hähnle2018-12-193-4/+4
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: don't set RAW_WAIT for CP DMA clearsNicolai Hähnle2018-12-191-1/+2
| | | | | | There is never a read-after-write hazard because the command doesn't read. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/gfx9: use SET_UCONFIG_REG_INDEX packets when availableNicolai Hähnle2018-12-192-5/+15
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: add si_init_draw_functions and make some functions staticNicolai Hähnle2018-12-194-22/+22
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: extract declare_vs_blit_inputsNicolai Hähnle2018-12-191-18/+25
| | | | | | Prepare for some later refactoring. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: move SI_FORCE_FAMILY functionality to winsysNicolai Hähnle2018-12-191-34/+0
| | | | | | | This helps some debugging cases by initializing addrlib with slightly more appropriate settings. Reviewed-by: Marek Olšák <[email protected]>
* r600: remove redundant semicolonNicolai Hähnle2018-12-191-1/+1
| | | | | Reviewed-By: Gert Wollny <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* meson: add etnaviv to the tools optionChristian Gmeiner2018-12-181-1/+2
| | | | | Signed-off-by: Christian Gmeiner <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* etnaviv: use surface format directlyLucas Stach2018-12-182-9/+4
| | | | | | | | There is no need to do the detour over the resource behind the surface to get the format. Use the surface format directly. Signed-off-by: Lucas Stach <[email protected]> Reviewed-by: Philipp Zabel <[email protected]>
* nir/opt_peephole_select: Don't peephole_select expensive math instructionsIan Romanick2018-12-172-2/+2
| | | | | | | | | | | | | | | | On some GPUs, especially older Intel GPUs, some math instructions are very expensive. On those architectures, don't reduce flow control to a csel if one of the branches contains one of these expensive math instructions. This prevents a bunch of cycle count regressions on pre-Gen6 platforms with a later patch (intel/compiler: More peephole select for pre-Gen6). v2: Remove stray #if block. Noticed by Thomas. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Thomas Helland <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* nir/opt_peephole_select: Don't try to remove flow control around indirect loadsIan Romanick2018-12-172-2/+2
| | | | | | | | | | | | | | | | | | | That flow control may be trying to avoid invalid loads. On at least some platforms, those loads can also be expensive. No shader-db changes on any Intel platform (even with the later patch "intel/compiler: More peephole select"). v2: Add a 'indirect_load_ok' flag to nir_opt_peephole_select. Suggested by Rob. See also the big comment in src/intel/compiler/brw_nir.c. v3: Use nir_deref_instr_has_indirect instead of deref_has_indirect (from nir_lower_io_arrays_to_elements.c). v4: Fix inverted condition in brw_nir.c. Noticed by Lionel. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* vc4: Reuse nir_format_convert.h in our blend lowering.Eric Anholt2018-12-171-33/+3
| | | | | These helpers came along after and have effectively the same implementation.
* nir: Add a bool to int32 lowering passJason Ekstrand2018-12-162-0/+4
| | | | | | | | We also enable it in all of the NIR drivers. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Tested-by: Bas Nieuwenhuizen <[email protected]>
* nir: Rename Boolean-related opcodes to include 32 in the nameJason Ekstrand2018-12-161-20/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a squash of a bunch of individual changes: nir/builder: Generate 32-bit bool opcodes transparently nir/algebraic: Remap Boolean opcodes to the 32-bit variant Use 32-bit opcodes in the NIR producers and optimizations Generated with a little hand-editing and the following sed commands: sed -i 's/nir_op_ball_fequal/nir_op_b32all_fequal/g' **/*.c sed -i 's/nir_op_bany_fnequal/nir_op_b32any_fnequal/g' **/*.c sed -i 's/nir_op_ball_iequal/nir_op_b32all_iequal/g' **/*.c sed -i 's/nir_op_bany_inequal/nir_op_b32any_inequal/g' **/*.c sed -i 's/nir_op_\([fiu]lt\)/nir_op_\132/g' **/*.c sed -i 's/nir_op_\([fiu]ge\)/nir_op_\132/g' **/*.c sed -i 's/nir_op_\([fiu]ne\)/nir_op_\132/g' **/*.c sed -i 's/nir_op_\([fiu]eq\)/nir_op_\132/g' **/*.c sed -i 's/nir_op_\([fi]\)ne32g/nir_op_\1neg/g' **/*.c sed -i 's/nir_op_bcsel/nir_op_b32csel/g' **/*.c Use 32-bit opcodes in the NIR back-ends Generated with a little hand-editing and the following sed commands: sed -i 's/nir_op_ball_fequal/nir_op_b32all_fequal/g' **/*.c sed -i 's/nir_op_bany_fnequal/nir_op_b32any_fnequal/g' **/*.c sed -i 's/nir_op_ball_iequal/nir_op_b32all_iequal/g' **/*.c sed -i 's/nir_op_bany_inequal/nir_op_b32any_inequal/g' **/*.c sed -i 's/nir_op_\([fiu]lt\)/nir_op_\132/g' **/*.c sed -i 's/nir_op_\([fiu]ge\)/nir_op_\132/g' **/*.c sed -i 's/nir_op_\([fiu]ne\)/nir_op_\132/g' **/*.c sed -i 's/nir_op_\([fiu]eq\)/nir_op_\132/g' **/*.c sed -i 's/nir_op_\([fi]\)ne32g/nir_op_\1neg/g' **/*.c sed -i 's/nir_op_bcsel/nir_op_b32csel/g' **/*.c Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Tested-by: Bas Nieuwenhuizen <[email protected]>
* vc4: Use the original bit size when scalarizing uniform loads.Eric Anholt2018-12-161-1/+2
| | | | | | Prevents a regression in jekstrand's 1-bit series. Reviewed-by: Jason Ekstrand <[email protected]>
* v3d: Drop in a bunch of notes about performance improvement opportunities.Eric Anholt2018-12-142-1/+13
| | | | | | These have all been floating in my head, and while I've thought about encoding them in issues on gitlab once they're enabled, they also make sense to just have in the area of the code you'll need to work in.
* v3d: Use the uniform pretty-printer in v3d_write_uniforms()'s debug code.Eric Anholt2018-12-141-1/+3
| | | | | This will be a lot easier than my usual "38400.000000? that looks like a viewport scale" decoding strategy.
* v3d: Move uinfo->data[] dereference to the top of v3d_write_uniforms().Eric Anholt2018-12-141-15/+13
| | | | | | Follows 3954331aff23 ("vc4: Pull uinfo->data[i] dereference out to the top of the loop.") which showed a large performance win for vc4, but also cleans up the code a decent bit.
* v3d: Add support for draw indirect for GLES3.1.Eric Anholt2018-12-142-2/+31
| | | | | | In trying to enable compute shaders, I found that a bunch of deqp-gles31's compute stuff wanted to interact with indirect dispatch. This was easy to do on its own.
* v3d: Add safety checks for resource_create().Eric Anholt2018-12-141-0/+6
| | | | This should ease my debugging next time I screw it up.
* v3d: Add support for texturing from linear.Eric Anholt2018-12-146-3/+110
| | | | | | | Just like vc4, we have to support linear shared BOs for X11 on arbitrary displays. When we're faced with a request to texture from one of those, make a shadow image that we copy using the TFU at the start of the draw call.
* v3d: Add support for using the TFU to do some blits.Eric Anholt2018-12-141-42/+129
| | | | This will be useful in particular for blits from raster to UIF for X11.
* v3d: Don't forget to bump the number of writes when doing TFU ops.Eric Anholt2018-12-141-0/+2
| | | | | | generatemipmap is just filling out the rest of the mipmap that's already been written (by a mapping or a draw call), so it didn't matter. As I reuse the TFU code for linear-to-UIF conversions, it'll start mattering.
* v3d: Set up the right stride for raster TFU.Eric Anholt2018-12-141-1/+1
| | | | | I didn't have any raster images in the generatemipmap path, so the pixels-vs-bytes mixup didn't matter here.
* v3d: Don't forget to wait for our TFU job before rendering from it.Eric Anholt2018-12-141-0/+8
| | | | | | | | Otherwise we may race to read old contents. This didn't show up in the CTS and piglit for me, but it did once I started using the TFU to do linear->UIF blits for X11. Fixes: 2ebca177dc18 ("v3d: Use the TFU to do generatemipmap.")
* nvc0: always keep TSC slot 0 bound to fix TXFIlia Mirkin2018-12-142-0/+21
| | | | | | | | | | | | Same as on nv50, the TXF op always uses the TSC bound to slot 0, returning blank values if nothing is bound. An earlier change arranges for the TSC entries list to always have valid data at entry 0, so here we just make use of it. Fixes arb_texture_buffer_object-subdata-sync among others. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: replace use of explicit default_tsc with entry 0Ilia Mirkin2018-12-146-22/+25
| | | | | | | | | | | This was used for implementing FBFETCH. However that uses TXF, which doesn't do much with a TSC. The only important bit is that sRGB-decoding works as expected, which we can achieve since all samplers we ever generate enable sRGB-decoding. Always point to entry 0 in the TSC table, and ensure that even before it ever gets initialized, the sRGB-decoding enable bit is set. Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/a6xx: fix corrupted uniformsRob Clark2018-12-141-1/+2
| | | | | | | | | | For older gen's fd_wfi() is used to conditionally insert a WFI if there hasn't already been one since last draw. But this doesn't work out well with stateobj since the order the stateobj is evaluated might not be what you expect. (Ie. stateobj might not be evaluated until a later draw if there is no geometry from the current draw in a given tile.) Signed-off-by: Rob Clark <[email protected]>
* etnaviv: drop redundant ctx function parameterChristian Gmeiner2018-12-141-4/+3
| | | | | | | | There is no need to have an extra ctx paramter as all the other parameters carry all the needed information. Signed-off-by: Christian Gmeiner <[email protected]> Reviewed-by: Lucas Stach <[email protected]>
* freedreno/a6xx: fix resource_copy_region()Rob Clark2018-12-131-9/+24
| | | | | | | | | | | | | | pctx->resource_copy_region() needs to fall back to sw copy for non-renderable formats. But previously for things that we could not use the blitter for, would fall back to 3d. Which won't work if 3d can't render to the dst format either. Instead rework things to fallback to fd_resource_copy_region(), which will try 3d core and then fall back to memcpy(). Fixes (for example) dEQP-GLES3.functional.texture.format.sized.2d.rgb9_e5_pot Signed-off-by: Rob Clark <[email protected]>
* freedreno: move fd_resource_copy_region()Rob Clark2018-12-133-62/+73
| | | | | | Code-motion prep for next patch. Signed-off-by: Rob Clark <[email protected]>
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