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* virgl: make transfer code with PIPE_BUFFER targetsGurchetan Singh2018-12-191-2/+4
* virgl: consolidate transfer codeGurchetan Singh2018-12-195-59/+73
* virgl: store layer_stride in metadataGurchetan Singh2018-12-192-6/+6
* virgl: move vrend_get_tex_image_offset to common codeGurchetan Singh2018-12-193-26/+28
* virgl: move virgl_resource_layout to common codeGurchetan Singh2018-12-193-42/+51
* virgl: move texture metadata to common codeGurchetan Singh2018-12-192-12/+18
* virgl: remove unnessecary codeGurchetan Singh2018-12-191-3/+0
* virgl: texture_transfer_pool --> transfer_poolGurchetan Singh2018-12-196-11/+11
* radeonsi: const-ify the si_query_opsNicolai Hähnle2018-12-193-5/+5
* radeonsi: split perfcounter queries from si_query_hwNicolai Hähnle2018-12-191-50/+93
* radeonsi: factor si_query_buffer logic out of si_query_hwNicolai Hähnle2018-12-194-110/+99
* radeonsi: move query suspend logic into the top-level si_query structNicolai Hähnle2018-12-193-44/+62
* radeonsi: move remaining perfcounter code into si_perfcounter.cNicolai Hähnle2018-12-197-766/+643
* radeonsi: track constant buffer bind history in si_pipe_set_constant_bufferNicolai Hähnle2018-12-191-2/+3
* radeonsi: use si_set_rw_shader_buffer for setting streamout buffersNicolai Hähnle2018-12-191-50/+11
* radeonsi: add an si_set_rw_shader_buffer convenience functionNicolai Hähnle2018-12-192-45/+64
* radeonsi: avoid using hard-coded SI_NUM_RW_BUFFERSNicolai Hähnle2018-12-191-1/+2
* radeonsi: show the fixed function TCS in debug dumpsNicolai Hähnle2018-12-191-2/+8
* radeonsi: const-ify si_set_tesseval_regsNicolai Hähnle2018-12-191-2/+2
* radeonsi: rename SI_RESOURCE_FLAG_FORCE_TILING to clarify its purposeNicolai Hähnle2018-12-193-4/+4
* radeonsi: don't set RAW_WAIT for CP DMA clearsNicolai Hähnle2018-12-191-1/+2
* radeonsi/gfx9: use SET_UCONFIG_REG_INDEX packets when availableNicolai Hähnle2018-12-192-5/+15
* radeonsi: add si_init_draw_functions and make some functions staticNicolai Hähnle2018-12-194-22/+22
* radeonsi: extract declare_vs_blit_inputsNicolai Hähnle2018-12-191-18/+25
* radeonsi: move SI_FORCE_FAMILY functionality to winsysNicolai Hähnle2018-12-191-34/+0
* r600: remove redundant semicolonNicolai Hähnle2018-12-191-1/+1
* meson: add etnaviv to the tools optionChristian Gmeiner2018-12-181-1/+2
* etnaviv: use surface format directlyLucas Stach2018-12-182-9/+4
* nir/opt_peephole_select: Don't peephole_select expensive math instructionsIan Romanick2018-12-172-2/+2
* nir/opt_peephole_select: Don't try to remove flow control around indirect loadsIan Romanick2018-12-172-2/+2
* vc4: Reuse nir_format_convert.h in our blend lowering.Eric Anholt2018-12-171-33/+3
* nir: Add a bool to int32 lowering passJason Ekstrand2018-12-162-0/+4
* nir: Rename Boolean-related opcodes to include 32 in the nameJason Ekstrand2018-12-161-20/+20
* vc4: Use the original bit size when scalarizing uniform loads.Eric Anholt2018-12-161-1/+2
* v3d: Drop in a bunch of notes about performance improvement opportunities.Eric Anholt2018-12-142-1/+13
* v3d: Use the uniform pretty-printer in v3d_write_uniforms()'s debug code.Eric Anholt2018-12-141-1/+3
* v3d: Move uinfo->data[] dereference to the top of v3d_write_uniforms().Eric Anholt2018-12-141-15/+13
* v3d: Add support for draw indirect for GLES3.1.Eric Anholt2018-12-142-2/+31
* v3d: Add safety checks for resource_create().Eric Anholt2018-12-141-0/+6
* v3d: Add support for texturing from linear.Eric Anholt2018-12-146-3/+110
* v3d: Add support for using the TFU to do some blits.Eric Anholt2018-12-141-42/+129
* v3d: Don't forget to bump the number of writes when doing TFU ops.Eric Anholt2018-12-141-0/+2
* v3d: Set up the right stride for raster TFU.Eric Anholt2018-12-141-1/+1
* v3d: Don't forget to wait for our TFU job before rendering from it.Eric Anholt2018-12-141-0/+8
* nvc0: always keep TSC slot 0 bound to fix TXFIlia Mirkin2018-12-142-0/+21
* nvc0: replace use of explicit default_tsc with entry 0Ilia Mirkin2018-12-146-22/+25
* freedreno/a6xx: fix corrupted uniformsRob Clark2018-12-141-1/+2
* etnaviv: drop redundant ctx function parameterChristian Gmeiner2018-12-141-4/+3
* freedreno/a6xx: fix resource_copy_region()Rob Clark2018-12-131-9/+24
* freedreno: move fd_resource_copy_region()Rob Clark2018-12-133-62/+73
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