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* ac,radeonsi: Always mark buffer stores as inaccessiblememonlyConnor Abbott2019-06-193-19/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | inaccessiblememonly means that it doesn't modify memory accesible via normal LLVM pointers. This lets LLVM's dead store elimination, memcpy forwarding, etc. ignore functions with this attribute. We don't represent descriptors as pointers, so this property is always true of buffer and image stores. There are plans to represent descriptors via pointers, but this just means that now nothing is inaccessiblememonly, as LLVM will then understand loads/stores via its usual alias analysis. Radeonsi was mistakenly only setting it if the driver could prove that there were no reads, and then it was cargo-culted into ac_llvm_build and ac_llvm_to_nir. Rip it out of everything. statistics with nir enabled: Totals from affected shaders: SGPRS: 152 -> 152 (0.00 %) VGPRS: 128 -> 132 (3.12 %) Spilled SGPRs: 0 -> 0 (0.00 %) Spilled VGPRs: 0 -> 0 (0.00 %) Private memory VGPRs: 0 -> 0 (0.00 %) Scratch size: 0 -> 0 (0.00 %) dwords per thread Code Size: 9324 -> 9244 (-0.86 %) bytes LDS: 2 -> 2 (0.00 %) blocks Max Waves: 17 -> 17 (0.00 %) Wait states: 0 -> 0 (0.00 %) The only difference was a manhattan31 shader. Acked-by: Timothy Arceri <[email protected]> Acked-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* panfrost: Move to use ralloc for some allocationsTomeu Vizoso2019-06-197-37/+44
| | | | | | | | | | | | | | We have some serious leaks, so plug some and also move to ralloc to limit the lifetime of some objects to that of their parent. Lots more such work to do. For some reason, this fixes: dEQP-GLES2.functional.lifetime.attach.deleted_output.texture_framebuffer Signed-off-by: Tomeu Vizoso <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* etnaviv: support GL_ARB_seamless_cubemap_per_textureChristian Gmeiner2019-06-192-5/+9
| | | | | | | Passes spec@amd_seamless_cubemap_per_texture@amd_seamless_cubemap_per_texture Signed-off-by: Christian Gmeiner <[email protected]> Reviewed-By: Guido Günther <[email protected]>
* etnaviv: update headers from rnndbChristian Gmeiner2019-06-196-22/+33
| | | | | | Update to etna_viv commit a3bf0da. Signed-off-by: Christian Gmeiner <[email protected]>
* radeonsi: fix undefined shift in macro definitionDave Airlie2019-06-191-1/+1
| | | | | | Pointed out by coverity Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* nouveau: fix frees in unsupported IR error paths.Dave Airlie2019-06-194-0/+6
| | | | | | | | This is pointless in that we won't ever hit those paths in real life, but coverity complains. Fixes: f014ae3c7cce ("nouveau: add support for nir") Reviewed-by: Ilia Mirkin <[email protected]>
* panfrost: Move clearing logic into pan_jobRohan Garg2019-06-183-48/+68
| | | | Reviewed-by: Alyssa Rosenzweig <[email protected]>
* virgl: fix sync issue regarding discard/unsync transfersChia-I Wu2019-06-181-5/+15
| | | | | | | | | | | | | | | | | | | | | | GL_MAP_INVALIDATE_BUFFER_BIT cannot be treated as GL_MAP_INVALIDATE_RANGE_BIT naively. When we run into ptr = glMapBufferRange(buf, 0, size, GL_WRITE_BIT|GL_MAP_INVALIDATE_BUFFER_BIT); memcpy(ptr, data1, size); glUnmapBuffer(buf); ptr = glMapBufferRange(buf, size, size, GL_WRITE_BIT|GL_MAP_UNSYNCHRONIZED_BIT); memcpy(ptr, data2, size); glUnmapBuffer(buf); we never want data1 to be copy_transfer'ed. Because that would mean that data2 might overwrite valid data. Signed-off-by: Chia-I Wu <[email protected]> Reviewed-by: Alexandros Frantzis [email protected] Fixes: a22c5df0794 ("virgl: Use buffer copy transfers to avoid waiting when mapping") Reviewed-by: Emil Velikov <[email protected]>
* panfrost: Enable sRGBAlyssa Rosenzweig2019-06-181-4/+0
| | | | | | | Now that sRGB formats are supported for both rendering and sampling, advertise support. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Disable AFBC on sRGB buffersAlyssa Rosenzweig2019-06-181-0/+7
| | | | | | | | The performance impact is slightly mitigated by tiling the render target, but it's undeniably still slow compared to AFBC. Unfortunately, it doesn't look like AFBC and sRGB play nice... Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Enable sRGB fixed-function blendingAlyssa Rosenzweig2019-06-182-3/+17
| | | | | | | | For fixed-function, we have hardware to handle sRGB so we just set a flag. For blend shaders, it's rather more involved; this is currently unimplemented. Assert it out for now; we don't need it quite yet. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Specify sRGB in the render targetAlyssa Rosenzweig2019-06-181-1/+4
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Implement sRGB texturingAlyssa Rosenzweig2019-06-181-1/+1
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Add sRGB render target flagAlyssa Rosenzweig2019-06-182-0/+2
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Implement tiled renderingAlyssa Rosenzweig2019-06-181-0/+4
| | | | | | | | We already can sample from Mali's linear/tiled encoding (the one from Utgard -- AFBC is mostly unrelated); let's be able to render to it as well. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Decode rendering block typeAlyssa Rosenzweig2019-06-183-7/+37
| | | | | | | A mode for rendering tiled/uncompressed was noticed, so we reshuffle the MFBD render target definitions to explicitly include block type. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Refactor texture targetsAlyssa Rosenzweig2019-06-186-27/+81
| | | | | | | | | | | | | | | | | This combines the two cmdstream bits "is_3d" and "is_not_cubemap" into a single 2-bit texture target selection, noticing it's the same as the 2-bit selection in Midgard and Bifrost texturing ops. Accordingly, we share this definition and add the missing entry for 1D/buffer textures. This requires a nontrivial (but functionally similar) refactor of all parts of the driver to use the new definitions appropriately. Theoretically, this should add support for buffer textures, but that's obviously not tested and probably wouldn't work. While doing so, we notice the sRGB enable bit, which we document and decode as well here so we don't forget about it. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Figure out job requirements in pan_job.cRohan Garg2019-06-183-8/+16
| | | | | | | | Requirements for a job should be figured out in pan_job.c v2: [Alyssa] Fix early return Reviewed-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Reset job counters once the job is submittedRohan Garg2019-06-182-5/+4
| | | | | | Move the reset out of frame invalidation into job submission Reviewed-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Initial implementation of panfrost_job_submitRohan Garg2019-06-183-5/+23
| | | | | | | | Start fleshing out panfrost_job v2: [Alyssa: Remove unused variable, warning introduced] Reviewed-by: Alyssa Rosenzweig <[email protected]>
* virgl_hw: add YUV supportGurchetan Singh2019-06-181-0/+6
| | | | | | Add corresponding entries from p_format.h Reviewed-by: Emil Velikov <[email protected]>
* virgl: sync to virglrenderer virgl_hw.hGurchetan Singh2019-06-181-3/+10
| | | | | | | It's nice to keep these two files in sync, as they define guest userspace <---> host userspace communcation. Reviewed-by: Emil Velikov <[email protected]>
* panfrost/midgard: Enable autovectorizationAlyssa Rosenzweig2019-06-181-2/+1
| | | | | | Enable nir_opt_vectorize. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Add support for TXS instructionsBoris Brezillon2019-06-183-2/+60
| | | | | | | | | | | | | This patch adds support for nir_texop_txs instructions which are needed to support the OpenGL textureSize() function. This is also needed to support RECT texture sampling which is currently lowered to 2D sampling + a TXS() instruction by the nir_lower_tex() helper. Changes in v2: * Split options for the 1st and 2nd tex lowering passes Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Prepare things to support non-native texture opsBoris Brezillon2019-06-181-16/+19
| | | | | | | | | We are about to add support for the TXS (texture size) op which is not implemented using a midgard texture instruction. Let's rename emit_tex() into emit_texop_native() and repurpose emit_tex() as a dispatcher. Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Move sysval upload logic out of panfrost_emit_for_draw()Boris Brezillon2019-06-182-17/+54
| | | | | | | | | | | | We're about to add more sysval types, and panfrost_emit_for_draw() is big enough, so let's move the sysval upload logic in a separate function. We also add one sub-function per sysval type to keep the panfrost_upload_sysvals() small/readable. Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Make the sysval logic more genericBoris Brezillon2019-06-181-22/+39
| | | | | | | | | | | We are about to add support for nir_texop_txs which requires adding a sysval/uniform containing the texture size. Let's change the emit_sysval_read() prototype to take a nir_instr object instead of a nir_intrinsic_instr one so we can re-use this function when emitting a sysval for a txs instruction. Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Adapt to constant name change in UABITomeu Vizoso2019-06-181-1/+1
| | | | | | | We hadn't updated the kernel header after the driver got into mainline. Signed-off-by: Tomeu Vizoso <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* panfrost: ci: Update resultsTomeu Vizoso2019-06-181-15/+0
| | | | | | | Alyssa fixed some failing tests last night. Signed-off-by: Tomeu Vizoso <[email protected]> Acked-by: Alyssa Rosenzweig <[email protected]>
* v3d: only flush jobs accessing the query BO when reading query resultsIago Toral Quiroga2019-06-181-2/+2
| | | | Reviewed-by: Eric Anholt <[email protected]>
* v3d: add a helper function to flush jobs using a BOIago Toral Quiroga2019-06-182-0/+12
| | | | | | v2: use _mesa_set_search() (Eric) Reviewed-by: Eric Anholt <[email protected]>
* iris: Support more RGBX pipe formats.Kenneth Graunke2019-06-171-2/+13
| | | | | | | | Without them, the state tracker falls back to an RGBA format, but it doesn't always manage to override the swizzle for us. So we lose the information that the API expects an X channel, where alpha is garbage and reads back as 1. We have no equivalent ISL RGBX format for these, so we just use RGBA directly and override the swizzle in all cases.
* iris: Make resource_copy_region handle packed depth-stencil resources.Kenneth Graunke2019-06-171-0/+10
| | | | | | Also copy along the separate stencil buffer if needed. Fixes Piglit's arb_copy_image-formats.
* iris: Order CS stall and TC invalidate for format reinterpretation hacksKenneth Graunke2019-06-171-3/+2
| | | | | | | | This should ensure the TC invalidate happens after the stall. Fixes KHR-GL43.copy_image.functional which does a CopyImage (blorp_copy) from a buffer (using R8G8B8A8_UINT), then GetTexImage to read back the original image (using R10G10B10A2_UNORM).
* iris: Be more aggressive at post-format-reintepret TC invalidate hackKenneth Graunke2019-06-171-8/+5
| | | | | | | | | | | | | | When copying/blitting with format reinterpretation, we invalidate the texture cache before/after. Before is so the source of the copy works, and after is to get rid of our new data in the "wrong" format to protect future attempts to sample. When I ported these hacks to iris, I tried to be cautious by only bothering with the hacks if the batch referenced the BO. This makes some sense for the before case. If it isn't referenced, the texture cache can't really have any data for the BO (since it's also invalidated between batches). But we still need to do the after case regardless, as we've just polluted the cache with hazardous entries.
* virgl: Assume sRGB write control for older guest kernels or virglrenderer hostsGert Wollny2019-06-171-1/+2
| | | | | | | | | | | | | | | | When the host virglrenderer is an older version that doesn't check the sRGB write control feature, or when the guest kernel doesn't support CAPS v2, then the guest will only report support for GL 2.1 on a GL 3.3 host, even though it was supporting 3.3 with earlier guest mesa versions. By also checking the host feature check version this regression can be avoided. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110921 Fixes: 2845939d6a72 virgl: Set sRGB write control CAP based on host capabilities Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Chia-I Wu <[email protected]>
* freedreno/a6xx: disallow UBWC for x24s8Rob Clark2019-06-171-4/+15
| | | | | | | | | Fixes: dEQP-GLES31.functional.stencil_texturing.format.depth24_stencil8_2d dEQP-GLES31.functional.stencil_texturing.format.stencil_index8_2d dEQP-GLES31.functional.stencil_texturing.misc.compare_mode_effect Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: un-swap X24S8_UINTRob Clark2019-06-172-5/+6
| | | | | | | | | | | | | | | | | | | The stencil is actually in the .w component, but we used to use SWAP to remap the channels. This doesn't work when tiled/ubwc. Fixes: dEQP-GLES31.functional.stencil_texturing.format.depth24_stencil8_2d_array dEQP-GLES31.functional.stencil_texturing.format.depth24_stencil8_cube dEQP-GLES31.functional.stencil_texturing.format.stencil_index8_2d_array dEQP-GLES31.functional.stencil_texturing.format.stencil_index8_cube dEQP-GLES31.functional.stencil_texturing.misc.base_level dEQP-GLES31.functional.texture.border_clamp.formats.stencil_index8.nearest_size_pot dEQP-GLES31.functional.texture.border_clamp.formats.stencil_index8.nearest_size_npot dEQP-GLES31.functional.texture.border_clamp.formats.depth24_stencil8_sample_stencil.nearest_size_pot dEQP-GLES31.functional.texture.border_clamp.formats.depth24_stencil8_sample_stencil.nearest_size_npot dEQP-GLES31.functional.texture.border_clamp.sampler.uint_stencil Signed-off-by: Rob Clark <[email protected]>
* llvmpipe: Don't use u_ringbuffer for lp_scene_queueCaio Marcelo de Oliveira Filho2019-06-171-36/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Inline the ring buffer and signal logic into lp_scene_queue instead of using a u_ringbuffer. The code ends up simpler since there's no need to handle serializing data from / to packets. This fixes a crash when compiling Mesa with LTO, that happened because of util_ringbuffer_dequeue() was writing data after the "header packet", as shown below struct scene_packet { struct util_packet header; struct lp_scene *scene; }; /* Snippet of old lp_scene_deque(). */ packet.scene = NULL; ret = util_ringbuffer_dequeue(queue->ring, &packet.header, sizeof packet / 4, return packet.scene; but due to the way aliasing analysis work the compiler didn't considered the "&packet->header" to alias with "packet->scene". With the aggressive inlining done by LTO, this would end up always returning NULL instead of the content read by util_ringbuffer_dequeue(). Issue found by Marco Simental and iThiago Macieira. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110884 Reviewed-by: Roland Scheidegger <[email protected]>
* panfrost/midgard: Simplify 2D array logicAlyssa Rosenzweig2019-06-171-4/+1
| | | | | | It shouldn't matter if we stick a z in for non-arrays, anyway. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Handle non-zero component in storeAlyssa Rosenzweig2019-06-172-8/+9
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Apply writemask to LUTsAlyssa Rosenzweig2019-06-172-3/+8
| | | | | | Fixes LUT instructions with NIR registers. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* amd: update addrlibMarek Olšák2019-06-171-0/+24
| | | | | Acked-by: Bas Nieuwenhuizen <[email protected]> Tested-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi: reduce MAX_GEOMETRY_OUTPUT_VERTICESNicolai Hähnle2019-06-171-1/+4
| | | | | | This fixes piglit [email protected]@gs-max-output on gfx9. Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* panfrost: Cleanup default blend modeAlyssa Rosenzweig2019-06-171-19/+8
| | | | | | | Just encode the Mali magic number for `replace` rather than awkwardly forcing Gallium structures through. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Don't accidentally include blend shaderAlyssa Rosenzweig2019-06-171-0/+2
| | | | | | Some residual dirty state can leak through across frames; zero this out. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Use typeless moves internallyAlyssa Rosenzweig2019-06-173-39/+15
| | | | | | | | We switch all fmov to (i)mov, following the NIR switch. This simplifies some code surrounding blend shaders and should have no functional changes elsewhere. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* virgl: better support for PIPE_TRANSFER_DISCARD_WHOLE_RESOURCEChia-I Wu2019-06-174-25/+92
| | | | | | | | | | | | | | | | | | | | | | | When the resource to be mapped is busy and the backing storage can be discarded, reallocate the backing storage to avoid waiting. In this new path, we allocate a new buffer, emit a state change, write, and add the transfer to the queue . In the PIPE_TRANSFER_DISCARD_RANGE path, we suballocate a staging buffer, write, and emit a copy_transfer (which may allocate, memcpy, and blit internally). The win might not always be clear. But another win comes from that the new path clears res->valid_buffer_range and does not clear res->clean_mask. This makes it much more preferable in scenarios such as access = enough_space ? GL_MAP_UNSYNCHRONIZED_BIT : GL_MAP_INVALIDATE_BUFFER_BIT; glMapBufferRange(..., GL_MAP_WRITE_BIT | access); memcpy(...); // append new data glUnmapBuffer(...); Signed-off-by: Chia-I Wu <[email protected]> Reviewed-by: Alexandros Frantzis <[email protected]>
* virgl: add virgl_rebind_resourceChia-I Wu2019-06-174-0/+148
| | | | | | | | | We are going support reallocating the HW resource for a virgl_resource. When that happens, the virgl_resource needs to be rebound to the context. Signed-off-by: Chia-I Wu <[email protected]> Reviewed-by: Alexandros Frantzis <[email protected]>
* virgl: save virgl_hw_res in virgl_transferChia-I Wu2019-06-175-14/+22
| | | | | | | | | | When PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE is properly supported, virgl_transfer might refer to a different virgl_hw_res than virgl_resource does. We need to save the virgl_hw_res and use the saved one. Signed-off-by: Chia-I Wu <[email protected]> Reviewed-by: Alexandros Frantzis <[email protected]>
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