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* etnaviv: Const-correctness etnaviv_emit.hWladimir J. van der Laan2017-11-221-1/+1
| | | | | | | | | The relocation structure is never changed by submitting it. Signed-off-by: Wladimir J. van der Laan <[email protected]> Reviewed-by: Philipp Zabel <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]> Signed-off-by: Lucas Stach <[email protected]>
* llvmpipe: fix snorm blendingRoland Scheidegger2017-11-212-28/+159
| | | | | | | | | | | | | | | | | | | The blend math gets a bit funky due to inverse blend factors being in range [0,2] rather than [-1,1], our normalized math can't really cover this. src_alpha_saturate blend factor has a similar problem too. (Note that piglit fbo-blending-formats test is mostly useless for anything but unorm formats, since not just all src/dst values are between [0,1], but the tests are crafted in a way that the results are between [0,1] too.) v2: some formatting fixes, and fix a fairly obscure (to debug) issue with alpha-only formats (not related to snorm at all), where blend optimization would think it could simplify the blend equation if the blend factors were complementary, however was using the completely unrelated rgb blend factors instead of the alpha ones... Reviewed-by: Jose Fonseca <[email protected]>
* r600: add cull distance supportDave Airlie2017-11-216-6/+24
| | | | | | This passes all the tests in piglit. Signed-off-by: Dave Airlie <[email protected]>
* broadcom/vc5: Align 1D texture miplevels to 64b.Eric Anholt2017-11-201-0/+2
| | | | Fixes tex-miplevel-selection GL2:texture() 1D
* broadcom/vc5: Clamp min lod to the last level.Eric Anholt2017-11-201-2/+3
| | | | | | Otherwise, the simulator would complain in tex-miplevel-selection that the min/max clamp was out of order. The actual HW seems to have clamped to the max anyway.
* broadcom/vc5: Increase simulator memory for tex-miplevel-selection.Eric Anholt2017-11-201-1/+1
| | | | | We were overflowing, because of all the little 4k allocations for CLs that were getting expanded to 128kb in the simulator due to the GMP alignment.
* swr/rast: Repair simd8 frontend code rotTim Rowley2017-11-201-1/+1
| | | | | | Keep non-default simd8 frontend code running for comparison purposes. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Implement AVX-512 GATHERPS in SIMD16 fetch shaderTim Rowley2017-11-204-29/+220
| | | | | | Disabled for now. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Simplify GATHER* jit builder apiTim Rowley2017-11-204-48/+48
| | | | | | | General cleanup, and prep work for possibly moving to llvm masked gather intrinsic. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Add alignment to transpose targetsTim Rowley2017-11-201-8/+8
| | | | | | | | Needed to ensure alignment for avx512. Fixes address sanitizer crash. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Cache eventmanagerTim Rowley2017-11-203-0/+9
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Enable AVX-512 targets in the jitterTim Rowley2017-11-202-10/+0
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Points with clipdistance can't go through simplepoints pathTim Rowley2017-11-201-1/+2
| | | | | | | Fixes piglit glsl-1.20:vs-clip-vertex-primitives and glsl-1.30:vs-clip-distance-primitives. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Code style change (NFC)Tim Rowley2017-11-201-2/+7
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Widen fetch shader to SIMD16Tim Rowley2017-11-205-3/+151
| | | | | | | Widen fetch shader to SIMD16, enable SIMD16 types in the jitter, and provide utility EXTRACT/INSERT SIMD8 <-> SIMD16 utility functions. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Support flexible vertex layout for DS outputTim Rowley2017-11-202-0/+3
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* gallium/u_threaded: avoid syncing in threaded_context_flushNicolai Hähnle2017-11-201-1/+2
| | | | | | | | We could always do the flush asynchronously, but if we're going to wait for a fence anyway and the driver thread is currently idle, the additional communication overhead isn't worth it. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: avoid syncing the driver thread in si_fence_finishNicolai Hähnle2017-11-202-37/+41
| | | | | | It is really only required when we need to flush for deferred fences. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: recompute the relative timeout after waiting for ready fenceNicolai Hähnle2017-11-201-0/+5
| | | | Reviewed-by: Marek Olšák <[email protected]>
* ddebug: fix the hang detection timeout calculationNicolai Hähnle2017-11-201-2/+2
| | | | | Fixes: c9fefa062b36 ("ddebug: rewrite to always use a threaded approach") Reviewed-by: Marek Olšák <[email protected]>
* ddebug: fix use-after-free of streamout targetsNicolai Hähnle2017-11-201-1/+1
| | | | | Fixes: b47727a83ad6 ("ddebug: implement pipelined hang detection mode") Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/gfx9: fix VM fault with fetched instance divisorsNicolai Hähnle2017-11-202-5/+12
| | | | | | | | | We need to account for SGPR locations in merged shaders. This case is exercised by KHR-GL45.enhanced_layouts.vertex_attrib_locations Fixes: 79c2e7388c7f ("radeonsi/gfx9: use SPI_SHADER_USER_DATA_COMMON") Reviewed-by: Marek Olšák <[email protected]>
* broadcom/vc5: Fix up integer texture handling.Eric Anholt2017-11-191-27/+28
| | | | | | | | The original spec I had didn't expose integer textures and suggested that you use unfiltered floats. Now there are proper formats for them. Fixes 16- and 32-bit texwrap integer tests in piglit, and dEQP-GLES3.functional.fbo.completeness.renderable.renderbuffer.color0.rgb10_a2ui.
* broadcom/vc5: Fix simulator assertion failures about color RT clears.Eric Anholt2017-11-191-2/+19
| | | | | | | | When we tried to clear color while storing depth, it assertion failed about basically not having enough information to decide which color RT to clear. It turns out the STORE_GENERAL picks the buffer according to the color buffer being stored, or all of them if NONE. If you're doing depth, it doesn't know which to pick.
* freedreno/ir3: add texture gather supportRob Clark2017-11-182-2/+17
| | | | Signed-off-by: Rob Clark <[email protected]>
* etnaviv: enable full overwrite when no color buffer is presentLucas Stach2017-11-182-3/+3
| | | | | | | | The OVERWRITE bit disables destination fetches, which is exactly what we want when there is no valid color buffer bound. Signed-off-by: Lucas Stach <[email protected]> Reviewed-by: Wladimir J. van der Laan <[email protected]>
* broadcom/vc5: Set up the padded height at surface creation time.Eric Anholt2017-11-173-16/+15
| | | | | This centralizes the calculation in the surface, instead of in each load/store.
* broadcom/vc5: Fix clear color for swap_color_rb render targets.Eric Anholt2017-11-171-0/+9
| | | | Fixes dEQP-GLES3.functional.depth_stencil_clear.depth.*
* broadcom/vc5: Fix pasteo in front stencil ref value setup.Eric Anholt2017-11-171-1/+1
| | | | Fixes piglit masked-clear.
* broadcom/vc5: Fix colormasking when we need to swap r/b colors.Eric Anholt2017-11-171-9/+24
| | | | Fixes part of piglit masked-clear.
* broadcom/vc5: Enable the Z min/max clipping planes.Eric Anholt2017-11-171-2/+0
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* broadcom/vc5: Fix driver for new PIPE_SHADER_CAP_MAX_HW_ATOMIC_*.Eric Anholt2017-11-171-0/+2
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* r300: add PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER* switch casesBrian Paul2017-11-171-0/+2
| | | | | | To silence compiler warnings. Reviewed-by: Marek Olšák <[email protected]>
* radeon/video: enable encode support for ravenBoyuan Zhang2017-11-171-1/+2
| | | | | | | Enable h.264 encode for vcn hardware (raven) Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* radeonsi: enable vcn encodeBoyuan Zhang2017-11-171-1/+3
| | | | | | | Enable vcn encode by creating radeon_encoder for vcn. Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* radeon/vcn: add create encoderBoyuan Zhang2017-11-171-1/+81
| | | | | | | Add implementation for create_encoder interface for vcn encode. Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* radeon/vcn: add encode get feedbackBoyuan Zhang2017-11-171-1/+14
| | | | | | | Add implementation for get_feedback interface for vcn encode. Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* radeon/vcn: add encode destroyBoyuan Zhang2017-11-171-1/+15
| | | | | | | Add implementation for destroy interface for vcn encode. Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* radeon/vcn: add encode end frameBoyuan Zhang2017-11-171-1/+2
| | | | | | | Add implementation for end_frame interface for vcn encode. Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* radeon/vcn: add encode bitstreamBoyuan Zhang2017-11-171-1/+13
| | | | | | | Add implementation for encode_bitstream interface for vcn encode. Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* radeon/vcn: add encode begin frameBoyuan Zhang2017-11-171-1/+22
| | | | | | | Add implementation for begin_frame interface for vcn encode. Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* radeon/vcn: add encode header implementationsBoyuan Zhang2017-11-172-0/+241
| | | | | | | | Implement encoding of sps, pps, and silce headers using the newly added h.264 header coding descriptors functions based on h.264 specs. Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* radeon/vcn: add encode header algorithmsBoyuan Zhang2017-11-172-0/+127
| | | | | | | | | | | | Since bitstream headers, e.g. sps, pps, slice, are encoded in driver side, we need to add corresponding algorithms that required to generate those headers. According to h.264 specs, signed/unsigned interger Exp-Golomb-coded syntax element with left bit first (code_se and code_ue) and unsigned integer using n bits (code_fixed_bits) descriptors function are needed. Therefore, adding those algorithms and related variables and output algorithms here. Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* radeon/vcn: add ib implementationsBoyuan Zhang2017-11-171-24/+268
| | | | | | | Implement required ibs and command buffer submission interfaces for vcn encode Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* radeon/vcn: add common encode partBoyuan Zhang2017-11-175-0/+489
| | | | | | | | | Add a skeleton pipe video interface and encode ib interface for video encode on vcn hardware. Add function defines and structures for vcn encode. Update Makefile.sources and meson.build with newly added files. Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* radeon/winsys: add vcn enc ring typeBoyuan Zhang2017-11-171-0/+1
| | | | | | | New ring type is needed for vcn encode Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* radeon/vcn: add vcn encode interfaceBoyuan Zhang2017-11-171-0/+325
| | | | | | | Add a new header file for vcn encode interface Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* freedreno/a5xx: stencil texturing supportRob Clark2017-11-173-10/+34
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx/gmem: fix z32/s8 restore/resolveRob Clark2017-11-171-5/+13
| | | | | | | BLIT_ZS mode is used for either combined z24/s8 or z32 in which case BLIT_S mode is used for separate stencil. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx/gmem: move ZS restore tiling hackRob Clark2017-11-171-20/+22
| | | | | | Code motion to simplify next patch. Signed-off-by: Rob Clark <[email protected]>
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