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* freedreno: use OUT_RELOCW when buffer is writtenRob Clark2014-05-211-4/+4
| | | | | | | These aren't buffers we ever read back from CPU, so using incorrect reloc fxn wasn't really harming anything. But might as well be correct. Signed-off-by: Rob Clark <[email protected]>
* rbug: add missing pipe->blit() entrypointRob Clark2014-05-211-0/+21
| | | | | Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Jakob Bornecrantz <[email protected]>
* nv50,nvc0: fix 3d blits with mipmap levelsIlia Mirkin2014-05-212-11/+19
| | | | | | | | | | Make sure to normalize the z coordinates as well as the x/y ones when there are mipmaps present. Fixes 3d mipmap generation, which now uses the blit path. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.2" <[email protected]> Reviewed-by: Ben Skeggs <[email protected]>
* nv50/ir: fix constant folding for OP_MUL subop HIGHIlia Mirkin2014-05-211-4/+43
| | | | | | | | | | | | These instructions can come in either through IMUL_HI/UMUL_HI TGSI opcodes, or from OP_DIV constant folding. Also make sure that the constant foldings which delete the original instruction still get counted as having done something. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.1 10.2" <[email protected]> Reviewed-by: Ben Skeggs <[email protected]>
* nv50/ir: fix s32 x s32 -> high s32 multiply logicIlia Mirkin2014-05-212-11/+82
| | | | | | | | | | | | | | | | | Retrieving the high 32 bits of a signed multiply is rather annoying. It appears that the simplest way to do this is to compute the absolute value of the arguments, and perform a u32 x u32 -> u64 operation. If the arguments' signs differ, then negate the result. Since there is no u64 support in the cvt instruction, we have the perform the 2's complement negation "by hand". This logic can come into use by the IMUL_HI instruction (very unlikely to be seen), as well as from constant folding of division by a constant. Fixes dolphin's divisions by 255. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.1 10.2" <[email protected]> Reviewed-by: Ben Skeggs <[email protected]>
* freedreno: don't advertise texture arrays for nowRob Clark2014-05-201-1/+1
| | | | | | | I think a3xx and later should support (it is part of GLES3), but this isn't needed for the time being and still needs to be reversed. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: shadow sampler supportRob Clark2014-05-192-3/+46
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx/compiler: refactor trans_samp()Rob Clark2014-05-191-47/+90
| | | | | | | Split it up into some smaller fxns so it doesn't grow into a huge monster as we add things. Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2014-05-194-4/+10
| | | | Signed-off-by: Rob Clark <[email protected]>
* llvmpipe: do IR counting for shader cache management after optimization.Roland Scheidegger2014-05-191-2/+2
| | | | | | | | | | | 2ea923cf571235dfe573c35c3f0d90f632bd86d8 had the side effect of IR counting now being done after IR optimization instead of before. Some quick analysis shows that there's roughly 1.5 times more IR instructions before optimization than after, hence the effective shader cache size got quite a bit smaller. Could counter this with an increase of the instruction limit but it probably makes more sense to count them after optimizations, so move that code. Reviewed-by: Brian Paul <[email protected]>
* nv50/ir: fix integer mul lowering for u32 x u32 -> high u32Ilia Mirkin2014-05-181-3/+4
| | | | | | | | | | | | UNION appears to expect that all of its sources are conditionally defined. Otherwise it inserts an unpredicated mov instruction which overwrites the desired result. This fixes tests that use UMUL_HI, and much less directly, unsigned integer division by a constant, which uses this functionality in a peephole pass. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.1 10.2" <[email protected]> Reviewed-by: Ben Skeggs <[email protected]>
* nv50/ir: make sure that texprep/texquerylod's args get coalescedIlia Mirkin2014-05-181-0/+2
| | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.2" <[email protected]> Reviewed-by: Ben Skeggs <[email protected]>
* freedreno/a3xx: use util_format_compose_swizzles()Rob Clark2014-05-181-9/+9
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx/compiler: 1D texturesRob Clark2014-05-181-4/+25
| | | | | | | | Gallium already gives us height==1 for these, so the texture state is already setup correctly to emulate 1D textures as a Nx1 2D texture. We just need to supply the .y coord. Signed-off-by: Rob Clark <[email protected]>
* freedreno: fix capsRob Clark2014-05-181-2/+2
| | | | | | In particular, we want mesa to emulate primitive restart for us. Signed-off-by: Rob Clark <[email protected]>
* freedreno: fix index buffer offsetRob Clark2014-05-181-1/+1
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: add sRBG texture supportRob Clark2014-05-162-0/+15
| | | | | | | That was easy. Turns out it is just a matter of setting one bit. Enable sampling from sRGB texture, and therefore enable GL 2.1 :-) Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2014-05-164-20/+21
| | | | Signed-off-by: Rob Clark <[email protected]>
* gallivm: give more verbose names to modulesRoland Scheidegger2014-05-167-16/+21
| | | | | | | | | When we had just one module "gallivm" was an appropriate name. But now we have modules containing all functions for a particular variant, so give it a corresponding name (this is really just for helping debugging). Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* gallium/radeon: link in libradeon.la at target levelEmil Velikov2014-05-153-20/+8
| | | | | | | | | | | | It makes more sense to link the core and common parts of the driver as the target is build. Additionally this will help us drop duplicating symbols for targets that static link mulitple pipe-drivers. Only egl-static needs that currently with more to come. To simplify things a bit add HAVE_GALLIUM_RADEON_COMMON variable. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* gallium/radeon: build only a single common library libradeonEmil Velikov2014-05-153-12/+5
| | | | | | | Just fold libllvmradeon in libradeon. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* freedreno/a3xx: fix write to bogus registerRob Clark2014-05-141-2/+2
| | | | | | | | | | | The loops for updating the multiple packed fields in SP_VS_OUT[] and SP_VS_VPC_DST[] will zero out one register beyond the last that on required. Which is normally not a problem (and is kinda convenient when looking at cmdstream dumps) unless we have maximum (16) varyings. Fix loop termination condition so that this does not happen. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: account for special inputs/outputsRob Clark2014-05-141-2/+2
| | | | | | | | | We need to size input/output tables big enough for special inputs/ outputs (gl_Position, gl_FrontFacing, etc) which, while they don't count towards the hw limit of 16 attributes or 16 varyings, we do still need to track them all the same. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: fix MAX_INPUTS shader capRob Clark2014-05-143-1/+9
| | | | | | | | | | Hardware only supports 16. Which fd3_shader_variant properly reflected, but the pipe cap did not, leading to array overflow (and shaders that could not possibly work). Also a bunch of asserts to make problems like this easier to see. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: add debug flag to expose glsl130Rob Clark2014-05-142-3/+8
| | | | | | | | | | We are starting to add integer support to the compiler, which does not get exercised with glsl feature level 120 and without advertising integer support. But doing so breaks too many things right now. So for now use a debug flag to conditionally expose the functionality while it is in development. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx/compiler: add KILL_IFRyan Houdek2014-05-141-1/+35
| | | | | | | | | The KILL_IF opcode could potentially be merged in to the regular KILL opcode function. It was a pain to do so, so I've left is separated for cleanliness. Signed-off-by: Ryan Houdek <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx/compiler: start adding integer supportRyan Houdek2014-05-141-0/+169
| | | | | | | | | | | | | Adds a large sum of TGSI opcodes to the a3xx compiler. For integer opcodes we have 28 opcodes added. Adds 4 floating point compare opcodes If GLSL 1.30 is enabled, this allows the GLSL 1.30 piglits to have a completion amount of 432/641. Signed-off-by: Ryan Houdek <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* llvmpipe: improve setup shader names (for debugging)Roland Scheidegger2014-05-151-38/+40
| | | | | | | | | | | | | The setup shaders were composed of both a fs shader number and a variant number. But since they aren't tied to a particular fragment shader, the former was a fixed zero while the latter was also always zero because it was never assigned. So, similar to what the fs code does, use a ever increasing number to give it a more catchy name (unlike fragment shaders though where this number is for each explicitly created shader, we just use it for the implicitly created variants). And while here, fix whitespace a bit. Reviewed-by: Jose Fonseca <[email protected]>
* llvmpipe: kill off llvmpipe_variant_countRoland Scheidegger2014-05-154-20/+4
| | | | | | | Unused except it was increased for both fs and setup shader variants created. Probably some leftover from ages ago. Reviewed-by: Jose Fonseca <[email protected]>
* nvc0: enable support for maxwell boardsBen Skeggs2014-05-155-19/+48
| | | | | Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: add maxwell (sm50) compiler backendBen Skeggs2014-05-1516-5/+3588
| | | | | | | | | | The big missing part here is proper sched data calculations, but hopefully the chosen placeholder will be sufficient for now. Passes piglit as well as GK107 does. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: maxwell isa has no per-instruction join modifierBen Skeggs2014-05-154-19/+23
| | | | | Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: replace immd 0 with $rLASTGPR for emit/restart opcodesBen Skeggs2014-05-151-0/+1
| | | | | Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: move nvc0 lowering pass class definitions into headerBen Skeggs2014-05-153-106/+136
| | | | | Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: bump sched data member to 32-bitsBen Skeggs2014-05-151-1/+1
| | | | | | | SM50 backend requires 21 bits per instruction, not 8. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: use vertex arrays for eng3d blitBen Skeggs2014-05-151-31/+64
| | | | | | | Maxwell doesn't have immediate-mode. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: restrict "constant vbo" logic to fermi/kepler classesBen Skeggs2014-05-151-1/+1
| | | | | Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: replace some vb->stride checks with constant_vbo insteadBen Skeggs2014-05-151-3/+3
| | | | | | | | Maxwell no longer has the methods to set constant attributes, and we'll want to be treating stride 0 vtxbufs the same as for stride > 0. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: add maxwell classBen Skeggs2014-05-152-0/+4
| | | | | Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: allow for easier modification of compiler library routinesBen Skeggs2014-05-1513-1057/+1057
| | | | | Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: properly distribute macros in source formBen Skeggs2014-05-155-244/+365
| | | | | Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* radeonsi: Fix anisotropic filtering state setupMichel Dänzer2014-05-143-13/+12
| | | | | | | | | | | | Bring it back in line with r600g. I broke this in the original radeonsi bringup. :( Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78537 Cc: "10.1 10.2" <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* llvmpipe: Delete unneeded LLVM stuff earlier.José Fonseca2014-05-147-34/+16
| | | | | | Same as Frank's change to draw module but for llvmpipe module. Reviewed-by: Roland Scheidegger <[email protected]>
* gallivm,draw,llvmpipe: Remove support for versions of LLVM prior to 3.1.José Fonseca2014-05-141-28/+0
| | | | | | | Older versions haven't been tested probably don't work anyway. But more importantly, code supporting it is hindering further work. Reviewed-by: Roland Scheidegger <[email protected]>
* freedreno/a3xx: occlusion query supportRob Clark2014-05-135-3/+185
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: add support for hw queriesRob Clark2014-05-1310-8/+734
| | | | | | | | | | | Real GPU queries need some infrastructure to track samples per tile and accumulate the results. But fortunately this can be shared across GPU generation. See: https://github.com/freedreno/freedreno/wiki/Queries#hardware-queries Signed-off-by: Rob Clark <[email protected]>
* freedreno/query: allow multiple query implementationsRob Clark2014-05-136-107/+269
| | | | | | | | Split out fd_query into an abstract base class, to allow multiple implementations. The current sw based queries are moved into fd_sw_query. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: add point-sizeRob Clark2014-05-131-4/+14
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2014-05-134-54/+252
| | | | Signed-off-by: Rob Clark <[email protected]>
* nv50,nvc0: fix blit 3d path for 1d array texturesIlia Mirkin2014-05-111-0/+6
| | | | | | | | | | Need to adjust coordinates since the shader receives the array index as depth in z, but the TEX instruction expects it to be the second coordinate for a 1D array texture. This fixes fbo-generatemipmap-array. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Ben Skeggs <[email protected]> Cc: "10.2" <[email protected]>
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