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* radeonsi: rename si_gfx_* functions to si_cp_*Marek Olšák2018-10-165-59/+59
| | | | and write_event_eop -> release_mem
* radeonsi: make si_gfx_write_event_eop more configurableMarek Olšák2018-10-165-15/+29
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* intel/nir, freedreno/ir3: Use the separated dead write vars passCaio Marcelo de Oliveira Filho2018-10-151-0/+1
| | | | | | | No changes to shader-db for intel. No changes to shader-db expected for freedreno. Reviewed-by: Jason Ekstrand <[email protected]>
* v3d: Add support for hardware pack/unpack of half floats.Eric Anholt2018-10-151-0/+1
| | | | | Cuts the formerly 7-minute simulation time of fs-packHalf2x16.shader_test in half.
* gallium/ttn: Convert inputs and outputs to derefs of variables.Eric Anholt2018-10-153-9/+10
| | | | | | | | | | | This means that TTN shaders more closely resemble GTN shaders: they have inputs and outputs as variable derefs, with the variables having their .driver_location already set up for you. This will be useful for v3d to do input variable DCE in NIR, which we can't do when the TTN shaders never have a pre-nir_lower_io stage. Acked-by: Rob Clark <[email protected]>
* freedreno/a6xx: Enable blitterKristian H. Kristensen2018-10-155-0/+623
| | | | | Signed-off-by: Kristian H. Kristensen <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno/a6xx: Update headersKristian H. Kristensen2018-10-151-16/+30
| | | | | Signed-off-by: Kristian H. Kristensen <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno/a6xx: Remove unnecessary GRAS_2D_BLIT_INFO writeKristian H. Kristensen2018-10-151-2/+0
| | | | | Signed-off-by: Kristian H. Kristensen <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* gallium/u_transfer_helper: Add support for separate Z24/S8 as well.Kenneth Graunke2018-10-143-3/+5
| | | | | | | | | | | | | | | | u_transfer_helper already had code to handle treating packed Z32_S8 as separate Z32_FLOAT and S8_UINT resources, since some drivers can't handle that interleaved format natively. Other hardware needs depth and stencil as separate resources for all formats. For example, V3D3 needs this for 24-bit depth as well. This patch adds a new flag to lower all depth/stencils formats, and implements support for Z24_UNORM_S8_UINT. (S8_UINT_Z24_UNORM is left as an exercise to the reader, preferably someone who has access to a machine that uses that format.) Reviewed-by: Eric Anholt <[email protected]>
* r600/sb: Fix constant-logical-operand warning.Vinson Lee2018-10-121-1/+1
| | | | | | | | | | | | | | | | | sb/sb_bc_parser.cpp:620:27: warning: use of logical '&&' with constant operand [-Wconstant-logical-operand] if (cf->bc.op_ptr->flags && FF_GDS) ^ ~~~~~~ sb/sb_bc_parser.cpp:620:27: note: use '&' for a bitwise operation if (cf->bc.op_ptr->flags && FF_GDS) ^~ & sb/sb_bc_parser.cpp:620:27: note: remove constant to silence this warning if (cf->bc.op_ptr->flags && FF_GDS) ~^~~~~~~~~ Fixes: da977ad90747 ("r600/sb: start adding GDS support") Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* svga: change svga_destroy_shader_variant() to return voidBrian Paul2018-10-095-23/+6
| | | | | | | | | | | | | svga_destroy_shader_variant() itself flushes and retries the command if there's a failure. So no need for the callers to do it. Other callers of the function were already ignoring the return value. This also fixes a corner-case double-free reported by Coverity (and reported by Dave Airlie). Tested with various OpenGL apps. Reviewed-by: Charmaine Lee <[email protected]>
* nvc0: fix blitting red to srgb8_alphaIlia Mirkin2018-10-091-0/+4
| | | | | | | | | | | | | For some reason the 2d engine can't handle this. Red formats get special treatment there, so perhaps related. Fixes dEQP-GLES3 tests of the form: dEQP-GLES3.functional.fbo.blit.conversion.r{8,16f,32f}_to_srgb8_alpha8 Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Karol Herbst <[email protected]> Cc: [email protected]
* nv50,nvc0: guard against zero-size blitsIlia Mirkin2018-10-092-0/+14
| | | | | | | | | | The current state tracker can generate these sometimes. Fixing this is more involved, and due to some integer math we can generate divisions-by-zero. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Karol Herbst <[email protected]> Cc: [email protected]
* nv50,nvc0: mark RGBX_UINT formats as renderableIlia Mirkin2018-10-091-4/+4
| | | | | | | | | | | | | | | | This helps st/mesa avoid some (apparently) buggy fallbacks. Specifically the CopyTexSubImage fallback tries to read texture A as RGBA_FLOAT and write back that data into the target format, which fails for integer formats which have no appropriate logic to do the conversion. Since integer formats don't blend, there's no harm in the fact that the "A" component gets written anyways. Fixes, among others: https://www.khronos.org/registry/webgl/sdk/tests/conformance2/textures/canvas/tex-2d-rgb8ui-rgb_integer-unsigned_byte.html Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* freedreno/a5xx+a6xx: fix LRZ pitch alignmentRob Clark2018-10-081-1/+1
| | | | | | | Both RB_2D_DST_SIZE.PITCH (a6xx) and RB_MRT[n].PITCH (a5xx) need alignment to 64. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: add LRZ supportRob Clark2018-10-088-132/+104
| | | | | | | | | | As with a5xx, hidden behind FD_MESA_DEBUG=lrz due to being paranoid about z-fighting issues with some games (in particular, this was observed with 0ad on a5xx.. but I think the proper solution to enable this by default is to figure out how to do driver specific driconf options). Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2018-10-087-38/+120
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: add helper for various CP_EVENT_WRITERob Clark2018-10-085-38/+30
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: remove unused fxnsRob Clark2018-10-082-19/+0
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: remove fd6_shader_stateobjRob Clark2018-10-083-23/+10
| | | | | | | Earlier gen's already got this cleanup, but a6xx was still off on a branch then. Signed-off-by: Rob Clark <[email protected]>
* util/u_queue: add UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITYMarek Olšák2018-10-061-1/+3
| | | | | Initial version discussed with Rob Clark under a different patch name. This approach leaves his driver unaffected.
* radeonsi: fix a typo at CS_PARTIAL_FLUSHMarek Olšák2018-10-061-1/+1
| | | | harmless
* ac: add ac_build_roundMarek Olšák2018-10-061-3/+1
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* ac: correct PKT3_COPY_DATA definitionsMarek Olšák2018-10-064-6/+6
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* ac: define all address spaces properlyMarek Olšák2018-10-061-3/+3
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* radeonsi:optimizing SET_CONTEXT_REG for shaders vgt_vertex_reuseSonny Jiang2018-10-054-2/+18
| | | | | Signed-off-by: Sonny Jiang <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* radeonsi:optimizing SET_CONTEXT_REG for shaders TessellationSonny Jiang2018-10-054-5/+26
| | | | | Signed-off-by: Sonny Jiang <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* radeonsi:optimizing SET_CONTEXT_REG for shaders PSSonny Jiang2018-10-053-14/+60
| | | | | Signed-off-by: Sonny Jiang <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* radeonsi:optimizing SET_CONTEXT_REG for shaders VSSonny Jiang2018-10-053-33/+77
| | | | | Signed-off-by: Sonny Jiang <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* radeonsi:optimizing SET_CONTEXT_REG for shaders GSSonny Jiang2018-10-054-24/+154
| | | | | Signed-off-by: Sonny Jiang <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* radeonsi: optimize and allow reg > 31 in radeon_opt_set_context_reg functionsMarek Olšák2018-10-051-22/+12
| | | | | | | reg_saved will have 64 bits, and (1 << reg) where reg > 31 has undefined behavior. (1ull << reg) would be correct for 64 bits. This commit shifts the other way in order to merge the conditions.
* radeonsi: optimizing SET_CONTEXT_REG for shaders ESSonny Jiang2018-10-055-10/+37
| | | | | Signed-off-by: Sonny Jiang <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* etnaviv: Use write combine instead of unached mappings for shader boGuido Günther2018-10-041-1/+1
| | | | | | | | | | The later are sensitive to unaligned accesses on arm64[1] and we don't need an uncached mapping here. [1]: https://lists.freedesktop.org/archives/etnaviv/2018-September/001956.html Signed-off-by: Guido Günther <[email protected]> Signed-off-by: Lucas Stach <[email protected]>
* freedreno: add the a6xx sources to the Android buildEmil Velikov2018-10-031-0/+1
| | | | | | | | | | | | Add the files otherwise things just won't build. Haven't actually tested it, but it's a small step in the right direction. Fixes: de3b34df973 ("freedreno: Add a6xx backend") Cc: Kristian H. Kristensen <[email protected]> Cc: Rob Clark <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* r600: use build-id when available for disk cacheTimothy Arceri2018-10-031-7/+7
| | | | Reviewed-by: Marek Olšák <[email protected]>
* nouveau: use build-id when available for disk cacheTimothy Arceri2018-10-031-7/+7
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: use build-id when available for disk cacheTimothy Arceri2018-10-031-12/+9
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: avoid sending GS_EMIT in shaders without outputsJózef Kucia2018-10-021-3/+6
| | | | | | | | | Fixes GPU hangs. Cc: 18.1 18.2 <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107857 Signed-off-by: Józef Kucia <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* radeonsi: initialize ac_gpu_info::name when using SI_FORCE_FAMILYMarek Olšák2018-10-021-0/+1
| | | | | so that it's not NULL when loading radeonsi and a GCN GPU is not present in the system.
* radeonsi: don't set the VS prolog key for the blit VSMarek Olšák2018-10-021-1/+2
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* freedreno/a6xx: hwbinningRob Clark2018-10-028-105/+159
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2018-10-027-41/+52
| | | | Signed-off-by: Rob Clark <[email protected]>
* radeonsi: add a workaround for bitfield_extract when count is 0Timothy Arceri2018-10-021-11/+30
| | | | | | | | | | | | | | | This ports the fix from 3d41757788ac. Both LLVM 7 & 8 continue to have this problem. It fixes rendering issues in some menu and loading screens of Civ VI which can be seen in the trace from bug 104602. Note: This does not fix the black triangles on Vega for bug 104602. Reviewed-by: Marek Olšák <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104602 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107276
* freedreno/a6xx: Build up draw dword0 outside visibilty if statementKristian H. Kristensen2018-09-271-17/+18
| | | | | | | | Pulling this logic out means we can share the logic and avoid a couple of temporary variables that helped make things clearer before. Note that in either vismode case, we always program vismode 0. Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno/a6xx: Simplify draw_emit() branches a bitKristian H. Kristensen2018-09-271-16/+8
| | | | | | | | Now that we've copied the emit logic into each branch of the if (info->index_size) statement, we can simplify the logic a bit according to which case we're in. Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno/a6xx: Copy OUT_RING() part into each branch of the index ifKristian H. Kristensen2018-09-271-17/+29
| | | | Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno/a6xx: Split fd6_draw_emit into direct and indirect pathsKristian H. Kristensen2018-09-271-36/+46
| | | | | | | This splits the two code paths into separate functions and moves the "if (info->indirect)" test into draw_impl(). Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno/a6xx: Inline fd6_draw()Kristian H. Kristensen2018-09-271-31/+17
| | | | | | Simplify the code a bit by inlining this helper. Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno/a6xx: Move emit_marker and wfi to draw_impl()Kristian H. Kristensen2018-09-271-17/+12
| | | | | | | This way the markers clearly bracket the draw call and isn't duplicated for both direct and indirect draw code. Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno/a6xx: Move inline functions out of fd6_draw.hKristian H. Kristensen2018-09-273-108/+110
| | | | | | Only used in fd6_draw.c so put them there. Signed-off-by: Kristian H. Kristensen <[email protected]>
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