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* radeonsi: fix stupid bug added in commit 07838603b9a69c05911edbcd351bfce5ad9b...Christian König2012-08-301-7/+8
* radeon/llvm: Fix encoding of FP immediates on SITom Stellard2012-08-291-1/+6
* radeon/llvm: Create a register class for the M0 registerTom Stellard2012-08-295-16/+24
* radeon/llvm: Set the neverHasSideEffects bit on more instructionsTom Stellard2012-08-291-0/+2
* radeon/llvm: Declare the interpolation intrinsics as ReadOnlyTom Stellard2012-08-293-3/+4
* radeon/llvm: Mark M0 as a def when lowering interpolation instructionsTom Stellard2012-08-291-4/+2
* radeon/llvm: Handle TGSI KIL opcode for SI.Michel Dänzer2012-08-283-0/+44
* radeon/llvm: Basic support for SI EXEC register.Michel Dänzer2012-08-283-2/+23
* radeonsi: Don't write to the PA_SC_RASTER_CONFIG register.Michel Dänzer2012-08-281-1/+0
* r600g: fix relative addressing on RS780 and RS880Marek Olšák2012-08-281-7/+6
* llvmpipe: Bump the maximum texture size (in pixels).José Fonseca2012-08-282-2/+9
* r300g: implement TRUNC correctlyMarek Olšák2012-08-274-1/+42
* radeonsi: Use FP16 shader export format when necessary / possible.Michel Dänzer2012-08-276-18/+114
* radeonsi: Refactor initialization of shader export intrinsic arguments.Michel Dänzer2012-08-271-36/+48
* radeonsi: Maintain cache of pixel shader variants according to contxt state.Michel Dänzer2012-08-276-59/+210
* radeonsi: Drop extraneous semicolons from pm4 state macro definitions.Michel Dänzer2012-08-271-3/+3
* r600g: implement compression for MSAA colorbuffers for evergreenMarek Olšák2012-08-2710-19/+479
* r600g: cleanup names around depth decompressionMarek Olšák2012-08-275-24/+24
* r600g: fix evergreen 8x MSAA sample positionsMarek Olšák2012-08-271-16/+16
* r600g: set CB_TARGET_MASK to 0xf and not 0xff for resolve on evergreenMarek Olšák2012-08-271-0/+1
* r300/compiler: Use variable lists in the rename_regs passTom Stellard2012-08-261-17/+14
* radeonsi: remove old tilling handlingChristian König2012-08-243-279/+31
* radeon/llvm: Cleanup R600Instructions.tdTom Stellard2012-08-242-93/+28
* radeon/llvm: Set End of Program bit on RAT instructionsTom Stellard2012-08-233-10/+14
* radeon/llvm: Use correct instruction for moving immediatesTom Stellard2012-08-231-1/+2
* radeon/llvm: Fix some coding style issuesTom Stellard2012-08-2314-82/+135
* radeon/llvm: Pull changes from external version of the backendTom Stellard2012-08-2321-76/+38
* radeon/llvm: Simplify the convert to ISA passTom Stellard2012-08-233-20/+7
* radeon/llvm: Make sure to use the Text section in the AsmPrinterTom Stellard2012-08-231-0/+2
* radeon/llvm: Use the MCCodeEmitter for R600Tom Stellard2012-08-2316-738/+779
* radeon/llvm: Use the MCCodeEmitter for SITom Stellard2012-08-2315-431/+591
* radeon/llvm: Set 64BitPtr feature bit for SITom Stellard2012-08-231-1/+1
* radeon/llvm: Lower RETFLAG DAG Node to S_ENDPGM on SITom Stellard2012-08-233-8/+12
* radeon/llvm: Add AsmPrinterTom Stellard2012-08-238-0/+193
* radeon/llvm: Mark JUMP as a pseudo instructionTom Stellard2012-08-231-1/+1
* radeon/llvm: Remove the last uses of MachineOperand flagsTom Stellard2012-08-232-8/+27
* radeon/llvm: Add flag operand to some instructionsTom Stellard2012-08-237-33/+97
* radeon/llvm: Encapsulate setting of MachineOperand flagsTom Stellard2012-08-234-50/+71
* radeonsi: rework vertex format handlingChristian König2012-08-221-10/+58
* radeonsi: fix SPI_PS_INPUT_ENA handlingChristian König2012-08-221-3/+14
* r600g: fix lockups with dual_src_blend v2Vadim Girlin2012-08-223-9/+45
* radeon/llvm: ExpandSpecialInstrs - Add support for cube instructionsTom Stellard2012-08-214-63/+100
* radeon/llvm: ExpandSpecialInstrs - Add support for vector instructionsTom Stellard2012-08-212-15/+30
* radeon/llvm: Add R600ExpandSpecialInstrs passTom Stellard2012-08-216-14/+112
* radeon/llvm: Add helper function for getting sub reg indicesTom Stellard2012-08-213-6/+19
* radeonsi: Handle NULL sampler views getting passed in by the state tracker.Michel Dänzer2012-08-212-5/+14
* radeon-llvm: Start multithreaded before using llvm.Mathias Fröhlich2012-08-201-0/+15
* r600g: Move common compute/3D register init to its own functionarchibald2012-08-203-170/+219
* nv50/ir/tgsi: handle DP2 in tgsi Instruction srcMaskChristoph Bumiller2012-08-181-0/+2
* nv50/ir/emit: don't forget saturation bit on f32 add immediateChristoph Bumiller2012-08-181-0/+2
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