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* r600g: enable SB backend by defaultVadim Girlin2013-08-304-5/+6
* r600g: fix color exports when we have no CBsVadim Girlin2013-08-301-3/+4
* nvc0/ir: Initialize NVC0LegalizePostRA member variables.Vinson Lee2013-08-291-1/+3
* radeonsi: Early return if no depth or stencil on release builds.Vinson Lee2013-08-291-0/+1
* freedreno: updates for msm drm/kms driverRob Clark2013-08-298-30/+55
* freedreno/a3xx/compiler: handle sync flags betterRob Clark2013-08-291-16/+34
* freedreno/a3xx/compiler: better const handlingRob Clark2013-08-291-90/+121
* radeonsi: Make sure libdrm_radeon headers are picked up from the right placeJonathan Gray2013-08-291-1/+2
* radeon/uvd: fix MPEG2/4 ref frame index limitChristian König2013-08-291-2/+2
* nouveau: Copy m4x4 and m8x8 separately.Vinson Lee2013-08-281-1/+2
* r300g: enable MSAA on r300-r400, be careful about using color compressionMarek Olšák2013-08-274-5/+14
* draw: clean up setting stream out information a bitRoland Scheidegger2013-08-276-29/+37
* llvmpipe: support nested/overlapping queries for all query typesRoland Scheidegger2013-08-273-18/+20
* softpipe: support nested/overlapping queries for all query typesRoland Scheidegger2013-08-272-18/+17
* svga: replace 0 with PIPE_OK in a few placesBrian Paul2013-08-263-5/+5
* radeonsi: Also set the depth component mask bit for stencil-only exportsMichel Dänzer2013-08-261-1/+4
* r600g: Implement the new float comparison instructions for Cayman as well.Henri Verbeet2013-08-251-4/+4
* nv30: add forgotten PIPE_CAP_CUBE_MAP_ARRAY cap to listIlia Mirkin2013-08-251-0/+1
* nouveau/video: avoid overwriting base codec init with templateIlia Mirkin2013-08-252-2/+2
* freedreno/a3xx: don't leak so muchRob Clark2013-08-241-0/+11
* freedreno/a3xx/compiler: fix SGT/SLT/etcRob Clark2013-08-241-29/+125
* freedreno/a3xx/compiler: bit of re-arrange/cleanupRob Clark2013-08-241-61/+71
* freedreno/a3xx/compiler: make compiler errors more usefulRob Clark2013-08-242-17/+33
* freedreno: fix segfault when no color buffer boundRob Clark2013-08-247-18/+40
* freedreno/a3xx/compiler: cat4 cannot use const reg as srcRob Clark2013-08-241-10/+27
* freedreno/a3xx/compiler: use max_reg rather than file_countRob Clark2013-08-241-7/+7
* freedreno/a3xx/compiler: handle saturate on dstRob Clark2013-08-241-0/+49
* freedreno/a3xx/compiler: fix CMPRob Clark2013-08-241-2/+2
* freedreno/a3xx: some texture fixesRob Clark2013-08-241-1/+24
* freedreno: update register headersRob Clark2013-08-248-111/+758
* freedreno: add debug option to disable scissor optimizationRob Clark2013-08-243-14/+22
* freedreno/a3xx: fix viewport on gmem->mem resolveRob Clark2013-08-241-0/+8
* freedreno/a3xx: fix color inversion on mem->gmem restoreRob Clark2013-08-241-3/+3
* radeonsi: Handle additional PIPE_COMPUTE_CAP_*Niels Ole Salscheider2013-08-231-1/+14
* radeonsi: copy r600_get_timestampNiels Ole Salscheider2013-08-231-0/+9
* radeonsi: Implement PIPE_QUERY_TIMESTAMPNiels Ole Salscheider2013-08-234-2/+46
* radeonsi: Fix y/z/w component values of TGSI_SEMANTIC_FOG pixel shader inputsMichel Dänzer2013-08-221-0/+18
* trace: Handle null tokens.José Fonseca2013-08-221-2/+6
* ilo: do not need last shader stage for 3DSTATE_SBEChia-I Wu2013-08-224-14/+6
* ilo: fix a potential issue with STATE_SIPChia-I Wu2013-08-221-2/+2
* ilo: add GEN check to 3DSTATE_CLIPChia-I Wu2013-08-221-0/+2
* svga: minor clean-ups in emit_hw_vs_vdecl()Brian Paul2013-08-211-6/+6
* gallivm: implement better control of per-quad/per-element/scalar lodRoland Scheidegger2013-08-201-4/+4
* radeonsi: Always pre-load separate VGPRs for centroid vs. center interpolationMichel Dänzer2013-08-201-1/+2
* radeonsi: Fix SPI_BARYC_CNTL register initializationMichel Dänzer2013-08-201-22/+3
* ilo: add ILO_DEBUG=flushChia-I Wu2013-08-2010-12/+29
* ilo: add ILO_DEBUG=drawChia-I Wu2013-08-205-2/+83
* r600g/sb: Move memsets of member structs to within constructor bodies.Vinson Lee2013-08-192-6/+3
* radeonsi: Ensure fmask_format is initialized in release builds.Vinson Lee2013-08-191-0/+1
* vl: add entrypoint to is_video_format_supportedChristian König2013-08-197-10/+17
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