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* r600g,radeonsi: set resource domains in one place (v2)Marek Olšák2014-02-065-27/+23
| | | | | | | v2: This doesn't change the behavior. It only moves the tiling check to r600_init_resource and removes the usage parameter. Reviewed-by: Christian König <[email protected]>
* radeon: just don't map VRAM buffers at allChristian König2014-02-061-2/+2
| | | | | Signed-off-by: Christian König <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeon/video: directly create buffers in the right domainChristian König2014-02-063-7/+12
| | | | | | Avoid moving things around on start of stream. Signed-off-by: Christian König <[email protected]>
* radeon/video: seperate common video functionsChristian König2014-02-069-315/+413
| | | | Signed-off-by: Christian König <[email protected]>
* r600g: add support for geom shaders to r600/r700 chipsets (v2)Dave Airlie2014-02-057-49/+313
| | | | | | | | | | | | | This is my first attempt at enabling r600/r700 geometry shaders, the basic tests pass on both my rv770 and my rv635, It requires this kernel patch: http://www.spinics.net/lists/dri-devel/msg52745.html v2: address Alex comments. Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600g: enable GLSL 3.30 on evergreen GPUsDave Airlie2014-02-051-1/+1
| | | | | | | This throws the switch to enable GL 3.3 and GLSL 330. Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600g: properly propogate clip dist write valueDave Airlie2014-02-051-0/+1
| | | | | | | | | | This moves the value from the GS shader to the copy shader so the registers are setup correctly. fixes tests/spec/glsl-1.50/execution/geometry/clip-distance-out-values.shader_test Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600g: calculate a better value for array_size (v2)Dave Airlie2014-02-051-1/+1
| | | | | | | | | attempt to calculate a better value for array size to avoid breaking apps. v2: use 0xfff like streamout, suggested by Grigori Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600g: fix CAYMAN geometry shader supportDave Airlie2014-02-051-2/+6
| | | | | | | | | cayman has a different end of program bit, so do that properly. fixes hangs with geom shader tests on cayman. Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600g: fix up shader out misc stuff for copy shaderDave Airlie2014-02-052-1/+16
| | | | | | | | | | | set the correct values so the misc out register is setup correctly for the copy shader. This also updates the state for the gs copy shader so the hw gets programmed correctly. Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600g: port the layered surface rendering patch from radeonsiDave Airlie2014-02-053-21/+19
| | | | | | | | | This just makes r600 and evergreen do what the radeonsi codepaths do for layered rendering. This makes the 2d amd_vertex_shader_layer test pass on evergreen. Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600g: initial VS output layer supportDave Airlie2014-02-054-14/+50
| | | | | | | This just adds support for emitting the proper value in the VS out misc. Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600g: setup const texture buffers for geom shadersDave Airlie2014-02-051-0/+6
| | | | | | | | This just enables the workarounds we have for vertex/pixel shaders for geom shaders as well. Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600g: calculate correct cut valueDave Airlie2014-02-051-1/+11
| | | | | | | This selects the cut value depending on the shader selected. Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600g: fix dynamic_input_array_index.shader_testDave Airlie2014-02-051-4/+44
| | | | | | | | | This follows what fglrx does, it unpacks the input we are going to indirect into a bunch of registers and indirects inside them. Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600g: add support for indirect geom ring writesDave Airlie2014-02-051-7/+58
| | | | | | | | | | | We need to be able to write to the ring using a base register for when we emit vertices in a loop, in theory the SB compiler could collapse these indirect writes to direct writes if the register value is constant and known, but that is outside my pay grade. Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600g: write proper output prim typeDave Airlie2014-02-052-27/+26
| | | | | | | | Vadim's code derived it from the info.mode, but it needs to be takes from the geometry shader output primitive. Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600g: enable instance cnt register with new enough kernelDave Airlie2014-02-051-6/+6
| | | | | | | | The instance cnt register was missing for a few kernels, with a new enough kernel we can output it. Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600g: add primitive input support for gsDave Airlie2014-02-054-1/+19
| | | | | | | only enable prim id if gs uses it Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600g: emit streamout from dma copy shaderDave Airlie2014-02-052-2/+8
| | | | | | | | This enables streamout with GS in the mix, from the VS dma shader. Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600g/gs: fix cases where number of gs inputs != number of gs outputsDave Airlie2014-02-051-1/+6
| | | | | | | this fixes a bunch of the geom shader built-in tests Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600g: increase array base for exported parametersDave Airlie2014-02-051-0/+3
| | | | | | | Trivial fix to Vadim's code. Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600g: initialise the geom shader loop registers.Dave Airlie2014-02-051-0/+2
| | | | | | | As we do for vertex and pixel shaders. Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600g: emit NOPs at end of shaders in more casesDave Airlie2014-02-051-2/+5
| | | | | | | | | | | If the shader has no CF clauses at all emit an nop If the last instruction is an ENDLOOP add a NOP for the LOOP to go to if the last instruction is CALL_FS add a NOP These fix a bunch of hangs in the geometry shader tests. Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600g: don't enable SB for geom shadersDave Airlie2014-02-051-0/+3
| | | | | | | | SB needs fixes for three GS instructions it seems to raise them outside loops etc despite my best efforts. Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600g/sb: add MEM_RING supportDave Airlie2014-02-054-5/+8
| | | | | | | | Although we don't use SB on geom shaders, the VS copy shader will use it so we might as well implement MEM_RING support in sb. Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600g: don't fail if we can't map VS->GS ring entriesDave Airlie2014-02-051-4/+3
| | | | | | | | This can happen in normal operation, so don't report an error on it, just continue. Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600g: initial support for geometry shaders on evergreen (v2)Vadim Girlin2014-02-0515-206/+909
| | | | | | | | | | | | | | This is Vadim's initial work with a few regression fixes squashed in. v2: (airlied) fix regression in glsl-max-varyings - need to use vs and ps_dirty fix regression in shader exports from rebasing. whitespace fixing. v2.1: squash fix assert Signed-off-by: Vadim Girlin <[email protected]> Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600g: add hw register definitions for GS block setupVadim Girlin2014-02-052-6/+75
| | | | | Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600g: defer shader variant selection and depending state updatesVadim Girlin2014-02-053-69/+57
| | | | | | | | [airlied: fix dropped streamout line - fix for master] Signed-off-by: Vadim Girlin <[email protected]> Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600g/bc: add support for indexed memory writes.Dave Airlie2014-02-053-4/+12
| | | | | | | It looks like we need these for geom shaders in the future. Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600g: move barrier and end_of_program bits from output to cf struct (v2)Vadim Girlin2014-02-054-30/+34
| | | | | | | | v2: fix regression on r600 NOP instructions. Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600g: split streamout emit code into a separate functionDave Airlie2014-02-051-103/+110
| | | | | | | | | For geometry shaders we need to call this code from a second place. Just move it out for now to keep future patches cleaner. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600g,radeonsi: skip unnecessary buffer_is_busy call, add a commentMarek Olšák2014-02-041-1/+5
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* r600g,radeonsi: skip busy-checking for DISCARD_RANGE if it has been done alreadyMarek Olšák2014-02-041-0/+4
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* r600g,radeonsi: treat DYNAMIC and STREAM usage as STAGINGMarek Olšák2014-02-041-7/+3
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* gallium: remove PIPE_CAP_MAX_COMBINED_SAMPLERSMarek Olšák2014-02-0412-29/+0
| | | | | | | This can be derived from the shader caps. All GPUs from ATI/AMD, NVIDIA, and INTEL have separate texture slots for each shader stage.
* radeon/uvd: fix feedback buffer handling v2Christian König2014-02-041-12/+28
| | | | | | | | | | | Without the correct feedback buffer size UVD runs into an error on each frame, reducing the maximum FPS. v2: fixing Michels comments Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Cc: "10.1" "10.0" "9.2" <[email protected]>
* freedreno: enabling binning and opt by defaultRob Clark2014-02-033-16/+11
| | | | | | | | | Hw binning pass doesn't seem to have broken anything. And optimizing compiler fixes a lot of shaders and doesn't seem to break anything. So re-org slightly FD_MESA_DEBUG params and make both hw binning and optimizer enabled by default. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx/compiler: new compilerRob Clark2014-02-0317-209/+2777
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new compiler generates a dependency graph of instructions, including a few meta-instructions to handle PHI and preserve some extra information needed for register assignment, etc. The depth pass assigned a weight/depth to each node (based on sum of instruction cycles of a given node and all it's dependent nodes), which is used to schedule instructions. The scheduling takes into account the minimum number of cycles/slots between dependent instructions, etc. Which was something that could not be handled properly with the original compiler (which was more of a naive TGSI translator than an actual compiler). The register assignment is currently split out as a standalone pass. I expect that it will be replaced at some point, once I figure out what to do about relative addressing (which is currently the only thing that should cause fallback to old compiler). There are a couple new debug options for FD_MESA_DEBUG env var: optmsgs - enable debug prints in optimizer optdump - dump instruction graph in .dot format, for example: http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot At this point, thanks to proper handling of instruction scheduling, the new compiler fixes a lot of things that were broken before, and does not appear to break anything that was working before[1]. So even though it is not finished, it seems useful to merge it in it's current state. [1] Not merged in this commit, because I'm not sure if it really belongs in mesa tree, but the following commit implements a simple shader emulator, which I've used to compare the output of the new compiler to the original compiler (ie. run it on all the TGSI shaders dumped out via ST_DEBUG=tgsi with various games/apps): https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12 Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx/compiler: split out old compilerRob Clark2014-02-036-1/+1531
| | | | | | | | For the time being, keep old compiler as fallback for things that the new compiler does not support yet. Split out as it's own commit to make the later new-compiler commits easier to follow. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx/compiler: prepare for new compilerRob Clark2014-02-039-146/+308
| | | | | | Shuffle things around to prepare for new compiler. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: remove useless reg tracking in disasm-a3xxRob Clark2014-02-031-174/+0
| | | | | | | Not really used for anything anymore. So strip it out and avoid conflicting symbols with upcoming new-compiler. Signed-off-by: Rob Clark <[email protected]>
* svga: check shader size against max command buffer sizeBrian Paul2014-02-032-12/+49
| | | | | | | If the shader is too large, plug in a dummy shader. This patch also reworks the existing dummy shader code. Reviewed-by: Jose Fonseca <[email protected]>
* svga: refactor some shader codeBrian Paul2014-02-0311-76/+171
| | | | | | | Put common code in new svga_shader.c file. Considate separate vertex/ fragment shader ID generation. Reviewed-by: Jose Fonseca <[email protected]>
* freedreno: better manage our WFI'sRob Clark2014-02-017-24/+36
| | | | | | | | Updates to non-banked registers, CP_LOAD_STATE, etc, need a WFI if there is potentially pending rendering. Track this better, and add fd_wfi() calls everywhere that might potentially need CP_WAIT_FOR_IDLE. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: add logicopRob Clark2014-02-013-6/+27
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: handle frag z writeRob Clark2014-02-017-25/+53
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: resync generated headersRob Clark2014-02-014-9/+39
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: fix const confusionRob Clark2014-02-012-9/+9
| | | | | | | | | | | | Gallium can leave const buffers bound above what is used by the current shader. Which can have a couple bad effects: 1) write beyond const space assigned, which can trigger HLSQ lockup 2) double emit of immed consts, first with bound const buffer vals followed by with actual immed vals. This seems to be a sort of undefined condition. Signed-off-by: Rob Clark <[email protected]>
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