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* r600g: report correct control flow depthMarek Olšák2013-02-061-2/+1
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* r300g: try to use color varyings for texcoords if max texcoord limit is exceededMarek Olšák2013-02-066-5/+71
| | | | +35 piglits
* r300/compiler: copy-propagate saturate mode when possibleMarek Olšák2013-02-061-2/+19
| | | | Reviewed-by: Tom Stellard <[email protected]>
* r300/compiler: add support for saturate output modifier in r500 vertex shadersMarek Olšák2013-02-062-10/+19
| | | | | | | The GLSL compiler can simplify clamp(v,0,1) to saturate. The state tracker doesn't use it yet, but it will. Reviewed-by: Tom Stellard <[email protected]>
* r300g: fix blending with RGBX formatsMarek Olšák2013-02-063-122/+202
| | | | Change DST_ALPHA to ONE.
* r300g: fix blending with blend color and RGBA formatsMarek Olšák2013-02-061-0/+11
| | | | NOTE: This is a candidate for the stable branches.
* svga: fix sRGB renderingBrian Paul2013-02-051-0/+11
| | | | | | | | | | | We weren't emitting the SVGA_RS_OUTPUTGAMMA state so sRGB rendering didn't work properly. Fixes piglit's framebuffer-srgb test. Note: This is a candidate for the stable branches. Reviewed-by: Jose Fonseca <[email protected]>
* r600g/compute: Fix segfault caused by new shader disassemblerTom Stellard2013-02-052-2/+4
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* radeonsi: default PA_SC_RASTER_CONFIG to 0Alex Deucher2013-02-041-1/+3
| | | | | | | | That should work in all cases. Signed-off-by: Alex Deucher <[email protected]> Note: this is a candidate for the 9.1 branch.
* radeonsi: add support for Oland chipsAlex Deucher2013-02-042-0/+4
| | | | | | Signed-off-by: Alex Deucher <[email protected]> Note: this is a candidate for the 9.1 branch
* gallium/drivers: handle PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED queryBrian Paul2013-02-048-0/+17
| | | | Initially, only softpipe/llvmpipe support SQRT.
* radeonsi: Remove spurious traces of R16G16B16 support.Michel Dänzer2013-02-041-3/+0
| | | | | | The hardware can't do it, and these were causing warnings in some piglit tests. NOTE: This is a candidate for the 9.1 branch.
* radeonsi: Enable texture arrays.Michel Dänzer2013-02-041-1/+1
| | | | | | 28/30 piglit tests pass. NOTE: This is a candidate for the 9.1 branch.
* radeonsi: Improve packing of texture address parameters.Michel Dänzer2013-02-041-30/+97
| | | | | | | In particular, the LOD bias and depth comparison values are packed before the 'normal' texture coordinates, and the array slice and LOD values are appended. NOTE: This is a candidate for the 9.1 branch.
* radeonsi: Adapt to sample intrinsics changes.Michel Dänzer2013-02-043-51/+56
| | | | | | Fix up intrinsic names, and bitcast texture address parameters to integers. NOTE: This is a candidate for the 9.1 branch.
* gallium: handle unhandled PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENTAndreas Boll2013-02-047-0/+8
| | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60098 Signed-off-by: Brian Paul <[email protected]>
* r600g: Fix memory leak.Vinson Lee2013-02-011-1/+3
| | | | | | | | Fixes resource leak defect reported by Coverity. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* nv30: Fix memory leak.Vinson Lee2013-02-011-0/+1
| | | | | | | Fixes resource leak defect reported by Coverity. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* nv50: Fix memory leak.Vinson Lee2013-02-011-0/+1
| | | | | | | Fixes resource leak defect reported by Coverity. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* nvc0: Fix memory leak.Vinson Lee2013-02-011-0/+1
| | | | | | | Fixes resource leak defect reported by Coverity. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* r600g/llvm: Select the correct GPU type for RV670Tom Stellard2013-02-011-1/+1
| | | | | | | | RV670 belongs in the R600 chip class https://bugs.freedesktop.org/show_bug.cgi?id=58666 NOTE: This is a candidate for the 9.1 branch
* radeonsi: Fix draws using user index buffer.Michel Dänzer2013-02-011-4/+3
| | | | | | | | | Was broken since commit bf469f4edc60bd1c5fd770cb231b8d5ab801427f ('gallium: add void *user_buffer in pipe_index_buffer'). Fixes 11 piglit tests and lots of missing geometry e.g. in TORCS. NOTE: This is a candidate for the 9.1 branch.
* svga: check for NaN shader immediatesBrian Paul2013-02-011-2/+4
| | | | | | | The svga device doesn't handle them. Replace with zeros. Fixes several piglit tests, such as "glsl-const-builtin-inversesqrt". Reviewed-by: Reviewed-by: José Fonseca <[email protected]>
* svga: add, use SVGA3D_SURFACE_HINT_VOLUME flagBrian Paul2013-02-012-0/+5
| | | | Reviewed-by: Reviewed-by: José Fonseca <[email protected]>
* trace: measure time for each gallium callBrian Paul2013-02-011-0/+24
| | | | | To get a rough idea of how much time is spent in each gallium driver function. The time is measured in microseconds.
* trace: add void to function definitionBrian Paul2013-02-011-1/+2
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* trace: allow GALLIUM_TRACE=stdout/stderrBrian Paul2013-02-011-3/+11
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* radeonsi: port some of get_shader_param changes from r600gMarek Olšák2013-02-011-6/+2
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* r300g: always put MSAA resources in VRAMMarek Olšák2013-02-011-3/+3
| | | | | | | | | This along with the latest drm-fixes branch should help with bad performance of MSAA. Remember: Nx MSAA can't be more than N times slower (where N=2,4,6). Anyway, I recommend at least 512 MB of VRAM for Full HD 6x MSAA. NOTE: This is a candidate for the 9.1 branch.
* r600g: remove broken assert from r600_isa.cVadim Girlin2013-02-011-2/+0
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* r600g: implement shader disassembler v3Vadim Girlin2013-02-013-4/+444
| | | | | | | | | | | | | | R600_DUMP_SHADERS environment var now allows to choose dump method: 0 (default) - no dump 1 - full dump (old dump) 2 - disassemble 3 - both v2: fix output for burst_count > 1 v3: use more human-readable output for kcache data in CF_ALU_xxx clauses, improve output for ALU_EXTENDED, other minor fixes Signed-off-by: Vadim Girlin <[email protected]>
* r600g: use tables with ISA info v3Vadim Girlin2013-02-0110-1789/+2378
| | | | | | | | | v3: added some flags including condition codes for ALU, fixed issue with CF reverse lookup (overlapping ranges of CF_ALU_xxx and other CF instructions) rebased on current master Signed-off-by: Vadim Girlin <[email protected]>
* r600g: add cs memory usage accounting and limit it v3Jerome Glisse2013-01-315-1/+59
| | | | | | | | | | | | | | | | | | | We are now seing cs that can go over the vram+gtt size to avoid failing flush early cs that goes over 70% (gtt+vram) usage. 70% is use to allow some fragmentation. The idea is to compute a gross estimate of memory requirement of each draw call. After each draw call, memory will be precisely accounted. So the uncertainty is only on the current draw call. In practice this gave very good estimate (+/- 10% of the target memory limit). v2: Remove left over from testing version, remove useless NULL checking. Improve commit message. v3: Add comment to code on memory accounting precision Signed-off-by: Jerome Glisse <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* r600g: fix htile buffer leakMarek Olšák2013-01-311-0/+1
| | | | NOTE: This is a candidate for the 9.1 branch.
* nv50,nvc0: fix/enable texture buffer objectsChristoph Bumiller2013-01-305-33/+42
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* llvmpipe: Don't advertise S8_UNORM (with feeble attempt at supporting it).José Fonseca2013-01-292-36/+46
| | | | | | | | | | | | | | S8_UNORM was inadvertedly supported together with Z16_UNORM. I tried to update the code to accomodate stencil-only -- it seemed a simple thing to do -- but "fbo-stencil clear GL_STENCIL_INDEX8" still fails, and it's not worth debugging. Therefore although this change tries to update for S8_UNORM, it also disables it completely. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* llvmpipe: Fix deferred depth writes for Z16_UNORM.José Fonseca2013-01-291-1/+6
| | | | | | | | | | This special path hadn't been exercised by my earlier testing, and mask values weren't being properly truncated to match the values. This change fixes that. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* llvmpipe: Support Z16_UNORM as depth-stencil format.José Fonseca2013-01-294-22/+43
| | | | | | | | | | Simply by adjusting the vector element width after/before reading/writing the depth-stencil values. Ran several GL_DEPTH_COMPONENT16 piglit tests without regressions. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* r600g: use uint64_t instead of unsigned long for proper 32bits cpu supportJerome Glisse2013-01-285-16/+16
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* r600g: real fix for non 3.8 kernelJerome Glisse2013-01-281-3/+5
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* r600g: fix segfault with old kernel9.1-branchpointJerome Glisse2013-01-285-11/+23
| | | | | | | Old kernel do not have dma support, patch pushed were missing some of the check needed to not use dma. Signed-off-by: Jerome Glisse <[email protected]>
* r600g: improve inputs/interpolation handling with llvm backendVadim Girlin2013-01-284-209/+151
| | | | | | | | | | Get rid of special handling for reserved regs. Use one intrinsic for all kinds of interpolation. v2[Vincent Lejeune]: Rebased against current master Reviewed-by: Tom Stellard <[email protected]> Signed-off-by: Vadim Girlin <[email protected]>
* r600g: Add ar_chan member to struct r600_bytecodeTom Stellard2013-01-283-0/+4
| | | | | | | | r600_bytecode::ar_chan stores the register channel for the value that will be loaded into the AR register. At the moment, this field is only used by the LLVM backend. The default backend always sets ar_chan = 0.
* r600g: More robust checks for MOVA_INT instructionsTom Stellard2013-01-281-8/+35
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* r600g/llvm: Add dummy export for vs outputVincent Lejeune2013-01-281-2/+20
| | | | | | Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=59588 Reviewed-by: Tom Stellard <[email protected]>
* r600g: Fix building with --enable-r600-llvm-compilerTom Stellard2013-01-281-3/+1
| | | | https://bugs.freedesktop.org/show_bug.cgi?id=59877
* r600g: don't emit WAIT_UNTIL on cayman/TN (v2)Alex Deucher2013-01-281-9/+28
| | | | | | | | | | | | | It shouldn't be needed and older kernels don't support it. v2: Replace with PS partial flush as before. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=59945 Signed-off-by: Alex Deucher <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* r600g: add async for staging buffer upload v2Jerome Glisse2013-01-2812-17/+595
| | | | | | v2: Add virtual address to dma src/dst offset for cayman Signed-off-by: Jerome Glisse <[email protected]>
* r600g: add multi ring support with dma as first second ring v4Jerome Glisse2013-01-2814-176/+327
| | | | | | | | | | | | | | | | | | | | | | | | | | | We keep track of ring emission order in a stack, whenever we need to flush we empty the stack in a fifo order. There is few helpers function for bo mapping and other ring activities that will make sure that the ring stack is properly flush and submitted. v2: fix st flush path, and other flush path to properly flush all rings if necessary v3: - improve name of ring helpers - make sure that each time a cs is gona be written it endup at top of the stack to avoid any issue such as : STACK[0] = dma (withbo A,B) STACK[1] = gfx (withbo C,D) Now if code try to emit a dma command relative to bo C or D it will start writting cmd stream into the cs and once it reach the point where it adds relocation it will flush. At that point the cs will have cmd that don't have proper relocation into the relocation buffer and kernel will just refuse to run. v4: - Drop the stack idea as it turn out there is no way to use it or benefit from it. Any time the driver start command on other ring, it always need to flush the previous ring. So make code simpler by not using a stack. Signed-off-by: Jerome Glisse <[email protected]>
* radeon/winsys: add dma ring support to winsys v3Jerome Glisse2013-01-283-3/+3
| | | | | | | | | | | | | | | | | | | | Add ring support, you can create a cs for each ring. DMA ring is bit special regarding relocation as you must emit as much relocation as there is use of the buffer. v2: - Improved comment on relocation changes - Use a single thread to queue cs submittion this simplify driver code while not impacting performances. Rational for this is that you have to wait for all previous submission to have completed so there was never a case while we could have 2 different thread submitting a command stream at the same time. This code just consolidate submission into one single thread per winsys. v3: - Do not use semaphore for empty queue signaling, instead use cond var. This is because it's tricky to maintain an even number of call to semaphore wait and semaphore signal (the number of cs in the stack would for instance make that number vary). Signed-off-by: Jerome Glisse <[email protected]>
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