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* vc4: Only update vc4->msaa when the framebuffer changes.Eric Anholt2015-12-151-7/+0
| | | | | | Any update here should have been the same as in vc4_set_framebuffer_state(), except for the point where vc4_blit.c temporarily sets different state for its different buffers.
* vc4: Don't consider nr_samples==1 surfaces to be MSAA.Eric Anholt2015-12-156-21/+25
| | | | | | This is apparently a weirdness of gallium -- nr_samples==1 is occasionally used and means the same thing as nr_samples==0. Fixes a bunch of ARB_framebuffer_srgb blit cases in piglit.
* vc4: Fix min() wrapper definition for the simulator's kernel code.Eric Anholt2015-12-151-1/+1
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* vc4: Warn instead of abort()ing on exec ioctl failures.Eric Anholt2015-12-151-3/+5
| | | | | | | | It's really harsh to abort() the X Server because of a momentary failure (particularly -ENOMEM). I don't see a way to pass an -ENOMEM up the stack from here, but we can at least log to stderr before proceeding on. Cc: "11.1" <[email protected]>
* radeonsi: fix perfcounter selection for SI_PC_MULTI_BLOCK layoutsNicolai Hähnle2015-12-151-1/+1
| | | | | | The incorrectly computed register count caused lockups. Reviewed-by: Edward O'Callaghan <[email protected]>
* gallium/radeon: remove unnecessary test in r600_pc_query_add_resultNicolai Hähnle2015-12-151-3/+0
| | | | | | | This test is a left-over of the initial development. It is unneeded and misleading, so let's get rid of it. Reviewed-by: Edward O'Callaghan <[email protected]>
* freedreno/a4xx: fix fragcoord.z + fragdepthRob Clark2015-12-152-5/+5
| | | | | | | | | | | | | It seems like disabling earlyz on a4xx also, by defaults, disables fragcoord.z to the FS. For frag shaders that both read fragcoord(.z) and write fragdepth, we need to set some extra bits to prevent a lockup. This lets us get rid of the hack of disabling fragcoord.z (which prevented 0ad from lockups, but resulted in rendering corruption). Also fixes fbo-depth-sample-compare. Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2015-12-156-92/+231
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3/cmdline: don't dump nir by defaultRob Clark2015-12-151-3/+1
| | | | | | By default we only want the disasm dumped, which we get anyways. Signed-off-by: Rob Clark <[email protected]>
* nvc0: check return value of nvc0_program_validate()Samuel Pitoiset2015-12-141-4/+1
| | | | | | | Spotted by Coverity. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50: check return value of nouveau_object_new()Samuel Pitoiset2015-12-141-4/+4
| | | | | | | When ret == 0, obj is not NULL. Spotted by Coverity. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50,nvc0: make use of unreachable() when invalid texture target happensSamuel Pitoiset2015-12-142-5/+2
| | | | | | | Spotted by Coverity. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* gk104/ir: simplify and fool-proof texbar algorithmIlia Mirkin2015-12-122-83/+56
| | | | | | | | | | | | | | With the current algorithm, we only look at tex uses. However there's a write-after-write hazard where we might decide to, on some path, not use a texture's output at all, but instead to write a different value to that register. However without the barrier, the texture might complete later and overwrite that value. This fixes Unreal Elemental demo on GK110/GK208, flightgear on GK10x, and likely other random-looking failures. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.1" <[email protected]>
* nv50/ir: combine sequences of conversionsIlia Mirkin2015-12-121-0/+43
| | | | | | | | | | In some cases shaders want non-default rounding when converting float to integer. This can be done in one go, so merge the two ops. This comes up in the packUnorm4x8 & co functions, as well as a few random shaders. Overall shader-db impact is minimal, helping a handful of witcher2 and other misc shaders. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: manually optimize multiplication expansion logicIlia Mirkin2015-12-121-6/+25
| | | | | | | | | | | | | | | | | | | | | | | | | The conversion of 32-bit integer multiplies into 16-bit ones happens after the regular optimization loop. However it's fairly common to multiply by a small integer, rendering some of the expansion pointless. Firstly, propagate immediates when possible into mul ops, secondly just remove the ops when they are unnecessary. Including the change to generate imad immediates, the effect is: total instructions in shared programs : 6365463 -> 6351898 (-0.21%) total gprs used in shared programs : 728684 -> 728684 (0.00%) total local used in shared programs : 9904 -> 9904 (0.00%) total bytes used in shared programs : 44001576 -> 44036120 (0.08%) local gpr inst bytes helped 0 0 3288 4 hurt 0 0 0 842 It's easy for this to hurt bytes since we end up always generating the 8-byte form, while we can't always get rid of the immediate in question. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: fix imul emission in the presence of an immediateIlia Mirkin2015-12-121-4/+7
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: teach post-ra immediate folding into mad about integersIlia Mirkin2015-12-121-3/+31
| | | | | | | There will usually be a split before the mad op, peer through that and pick out the right word of the immediate. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: add short imad supportIlia Mirkin2015-12-123-22/+40
| | | | | | | Support emission of the short imad, but also include it in the various logic that tries to make it possible to emit. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: can't have predication and immediatesIlia Mirkin2015-12-121-0/+3
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.0 11.1" <[email protected]>
* nv50/ir: fix texture grad for cubemapsIlia Mirkin2015-12-124-7/+6
| | | | | | We were ignoring the partial derivatives on the last dim. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: fix assumption that prog->maxGPR is in 32-bit reg unitsIlia Mirkin2015-12-122-4/+21
| | | | | | | On NV50, we use 16-bit reg units (to make it all work with half-regs). A few places assumed that it was always in 32-bit units. Signed-off-by: Ilia Mirkin <[email protected]>
* gallium/ddebug: regularly log the total number of draw callsNicolai Hähnle2015-12-121-0/+3
| | | | | | | | | | This helps in the use of GALLIUM_DDEBUG_SKIP: first run a target application with skip set to a very large number and note how many draw calls happen before the bug. Then re-run, skipping the corresponding number of calls. Despite the additional run, this can still be much faster than not skipping anything. Reviewed-by: Marek Olšák <[email protected]>
* gallium/ddebug: add GALLIUM_DDEBUG_SKIP optionNicolai Hähnle2015-12-123-15/+36
| | | | | | | | When we know that hangs occur only very late in a reproducible run (e.g. apitrace), we can save a lot of debugging time by skipping the flush and hang detection for earlier draw calls. Reviewed-by: Marek Olšák <[email protected]>
* llvmpipe: fix layer/vp input into fs when not written by prior stagesRoland Scheidegger2015-12-128-53/+96
| | | | | | | | | | | | | | | | | | | | | | | | | ARB_fragment_layer_viewport requires that if a fs reads layer or viewport index but it wasn't output by gs (or vs with other extensions), then it reads 0. This never worked for llvmpipe, and is surprisingly non-trivial to fix. The problem is the mechanism to handle non-existing outputs in draw is rather crude, it will simply redirect them to whatever is at output 0, thus later stages will just get garbage. So, rather than trying to fix this up (which looks non-trivial), fix this up in llvmpipe setup by detecting this case there and output a fixed zero directly. While here, also optimize the hw vertex layout a bit - previously if the gs outputted layer (or vp) and the fs read those inputs, we'd add them twice to the vertex layout, which is unnecessary. And do some minor cleanup, slots don't require that many bits, there was some bogus (but harmless) float/int mixup for psize slot too, make the slots all unsigned (we always put pos at pos zero thus everything else has to be positive if it exists), and make sure they are properly initialized (layer and vp index slot were not which looked fishy as they might not have got set back to zero when changing from a gs which outputs them to one which does not). This fixes the failures in piglit's arb_fragment_layer_viewport group (3 each for layer and vp). Reviewed-by: Jose Fonseca <[email protected]>
* svga: avoid emitting redundant SetSamplers() commandsBrian Paul2015-12-112-7/+18
| | | | | | | | This greatly reduces the number of SetSamplers() commands for some applications. Reviewed-by: José Fonseca <[email protected]> Reviewed-by: Charmaine Lee <[email protected]>
* svga: avoid emitting redundant SetIndexBuffer commandsBrian Paul2015-12-112-5/+16
| | | | | Reviewed-by: Charmaine Lee <[email protected]> Reviewed-by: José Fonseca <[email protected]>
* vc4: Add quick algebraic optimization for clamping of unpacked values.Eric Anholt2015-12-111-0/+18
| | | | | | | | | | | | | | | | GL likes to saturate your incoming color, but if that color's coming from unpacking from unorms, there's no point. Ideally we'd have a range propagation pass that cleans these up in NIR, but that doesn't seem to be going to land soon. It seems like we could do a one-off optimization in nir_opt_algebraic, except that doesn't want to operate on expressions involving unpack_unorm_4x8, since it's sized. total instructions in shared programs: 87879 -> 87761 (-0.13%) instructions in affected programs: 6044 -> 5926 (-1.95%) total estimated cycles in shared programs: 349457 -> 349252 (-0.06%) estimated cycles in affected programs: 6172 -> 5967 (-3.32%) No SSPD on openarena (which had the biggest gains, in its VS/CSes), n=15.
* vc4: When doing algebraic optimization into a MOV, use the right MOV.Eric Anholt2015-12-111-1/+6
| | | | | If there were src unpacks, changing to the integer MOV instead of float (for example) would change the unpack operation.
* vc4: Fix handling of src packs on in qir_follow_movs().Eric Anholt2015-12-111-2/+8
| | | | | | The caller isn't going to expect it from a return, so it would probably get misinterpreted. If the caller had an unpack in its reg, that's fine, but don't lose track of it.
* vc4: Add missing progress note in opt_algebraic.Eric Anholt2015-12-111-0/+1
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* vc4: Add debugging of the estimated time to run the shader to shader-db.Eric Anholt2015-12-113-17/+50
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* vc4: Fix handling of sample_mask output.Eric Anholt2015-12-112-6/+6
| | | | | | | I apparently broke this in a late refactor, in such a way that I decided its tests were some of those interminable ones that I should just blacklist from my testing. As a result, the refactors related to it were totally wrong.
* softpipe: enable GL_ARB_viewport_array support, update GL3.txt docEdward O'Callaghan2015-12-111-1/+1
| | | | | Signed-off-by: Edward O'Callaghan <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* softpipe: implement some support for multiple viewportsEdward O'Callaghan2015-12-118-52/+112
| | | | | | | | Mostly related to making sure the rasterizer can correctly pick out the correct scissor box for the current viewport. Signed-off-by: Edward O'Callaghan <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* gallium/radeon: remove radeon_winsys_cs_handleMarek Olšák2015-12-1135-137/+110
| | | | | | | | "radeon_winsys_cs_handle *cs_buf" is now equivalent to "pb_buffer *buf". Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: implement fast stencil clearMarek Olšák2015-12-114-23/+53
| | | | Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: re-enable Hyper-Z for stencilMarek Olšák2015-12-111-9/+3
| | | | Reviewed-by: Alex Deucher <[email protected]>
* r600g: remove a Hyper-Z workaround that's likely not needed anymoreMarek Olšák2015-12-111-19/+7
| | | | | | FORCE_OFF == 0, no need to set that Reviewed-by: Alex Deucher <[email protected]>
* r600g: re-enable Hyper-Z for stencil on Evergreen & CaymanMarek Olšák2015-12-111-4/+1
| | | | Reviewed-by: Alex Deucher <[email protected]>
* gallium/radeon: fix Hyper-Z hangs by programming PA_SC_MODE_CNTL_1 correctlyMarek Olšák2015-12-113-5/+18
| | | | | | | | | | This is the recommended setting according to hw people and it makes Hyper-Z stable. Just the two magic states. This fixes Evergreen, Cayman, SI, CI, VI (using the Cayman code). Cc: 11.0 11.1 <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: don't use the CP DMA workaround on Fiji and newerMarek Olšák2015-12-111-16/+20
| | | | Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: apply the streamout workaround to Fiji as wellMarek Olšák2015-12-111-1/+3
| | | | | Cc: 11.0 11.1 <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: also print hexadecimal values for register fields in the IB parserMarek Olšák2015-12-111-4/+7
| | | | | Reviewed-by: Michel Dänzer <[email protected] Reviewed-by: Edward O'Callaghan <[email protected]>
* radeonsi: implement RB+ for Stoney (v2)Marek Olšák2015-12-115-2/+170
| | | | | | v2: fix dual source blending Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: don't call of u_prims_for_vertices for patches and rectanglesMarek Olšák2015-12-111-1/+13
| | | | | | | | | Both caused a crash due to a division by zero in that function. This is an alternative fix. Cc: 11.0 11.1 <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]>
* radeonsi: use tgsi_shader_info::colors_writtenMarek Olšák2015-12-113-11/+1
| | | | Reviewed-by: Alex Deucher <[email protected]>
* r600g: write all MRTs only if there is exactly one output (fixes a hang)Marek Olšák2015-12-111-1/+2
| | | | | | | | This fixes a hang in piglit/arb_blend_func_extended-fbo-extended-blend-pattern_gles2 on REDWOOD. Cc: 11.0 11.1 <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* Revert "radeonsi: disable DCC on Stoney"Marek Olšák2015-12-111-4/+0
| | | | | | | | | | | This reverts commit 32f05fadbbdf2a3fb60055e610bbbdcd82dd3ce5. It turned out the problem with Stoney was caused by incorrect handling of a non-power-two VRAM size in the kernel driver. This is an optional BIOS setting and can be worked around by choosing a different VRAM size in the BIOS. Cc: 11.1 <[email protected]>
* r600: add missing return value check.Dave Airlie2015-12-111-0/+2
| | | | | | Pointed out by coverity scan. Signed-off-by: Dave Airlie <[email protected]>
* nir: Get rid of *_indirect variants of input/output load/store intrinsicsJason Ekstrand2015-12-105-66/+118
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is some special-casing needed in a competent back-end. However, they can do their special-casing easily enough based on whether or not the offset is a constant. In the mean time, having the *_indirect variants adds special cases a number of places where they don't need to be and, in general, only complicates things. To complicate matters, NIR had no way to convdert an indirect load/store to a direct one in the case that the indirect was a constant so we would still not really get what the back-ends wanted. The best solution seems to be to get rid of the *_indirect variants entirely. This commit is a bunch of different changes squashed together: - nir: Get rid of *_indirect variants of input/output load/store intrinsics - nir/glsl: Stop handling UBO/SSBO load/stores differently depending on indirect - nir/lower_io: Get rid of load/store_foo_indirect - i965/fs: Get rid of load/store_foo_indirect - i965/vec4: Get rid of load/store_foo_indirect - tgsi_to_nir: Get rid of load/store_foo_indirect - ir3/nir: Use the new unified io intrinsics - vc4: Do all uniform loads with byte offsets - vc4/nir: Use the new unified io intrinsics - vc4: Fix load_user_clip_plane crash - vc4: add missing src for store outputs - vc4: Fix state uniforms - nir/lower_clip: Update to the new load/store intrinsics - nir/lower_two_sided_color: Update to the new load intrinsic NIR and i965 changes are Reviewed-by: Kenneth Graunke <[email protected]> NIR indirect declarations and vc4 changes are Reviewed-by: Eric Anholt <[email protected]> ir3 changes are Reviewed-by: Rob Clark <[email protected]> NIR changes are Acked-by: Rob Clark <[email protected]>
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