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* nv50,nvc0: make sure to pushbuf_refn before putting bo into pushbuf_dataIlia Mirkin2015-06-234-0/+4
* nvc0: always put all tfb bufs into bufctxIlia Mirkin2015-06-231-3/+4
* ilo: emit 3DPRIMITIVE from gen6_3dprimitive_infoChia-I Wu2015-06-2211-87/+91
* ilo: align vertex buffer size in buf_create()Chia-I Wu2015-06-222-19/+20
* ilo: move ilo_format.[ch] out of coreChia-I Wu2015-06-225-8/+8
* ilo: add ilo_state_surface_valid_format()Chia-I Wu2015-06-224-284/+364
* ilo: add ilo_state_vf_valid_element_format()Chia-I Wu2015-06-223-124/+132
* nvc0: use NV_VRAM_DOMAIN() macroAlexandre Courbot2015-06-2211-22/+27
* nouveau: support for custom VRAM domainsAlexandre Courbot2015-06-222-0/+14
* ilo: add ilo_state_computeChia-I Wu2015-06-228-92/+586
* r600g: ignore sampler views for now.Dave Airlie2015-06-221-0/+1
* freedreno/ir3: pass sz to split_dest()Rob Clark2015-06-212-5/+7
* freedreno/ir3/nir: add more opcodesRob Clark2015-06-211-1/+8
* freedreno/ir3: only unminify txf coords on a3xxRob Clark2015-06-211-1/+9
* freedreno: remove int sampler shader variantsRob Clark2015-06-218-104/+7
* freedreno/ir3: block reshuffling and loops!Rob Clark2015-06-2110-126/+1025
* freedreno/ir3: a4xx encodes larger immed offsetRob Clark2015-06-214-7/+21
* freedreno/ir3: simplify find_neighbors stop conditionRob Clark2015-06-211-17/+1
* freedreno/ir3: move inputs/outputs to shaderRob Clark2015-06-2112-176/+160
* freedreno/ir3/ra: use register_allocateRob Clark2015-06-216-481/+590
* freedreno/ir3: introduce ir3_compiler objectRob Clark2015-06-2112-31/+90
* freedreno/ir3: dump nocp optionRob Clark2015-06-213-8/+0
* freedreno/ir3: silence warningsRob Clark2015-06-211-1/+10
* freedreno/ir3: remove tgsi f/eRob Clark2015-06-2112-3957/+25
* freedreno/ir3/sched: convert to priority queueRob Clark2015-06-214-229/+242
* freedreno/ir3: use standard list implementationRob Clark2015-06-218-209/+161
* freedreno/ir3: drop dot graph dumpingRob Clark2015-06-2110-525/+228
* freedreno/ir3: more builder helpersRob Clark2015-06-214-21/+16
* vc4: Use a defined t value for 1D textures.Eric Anholt2015-06-201-1/+3
* vc4: Fix write-only texsubimage when we had to align.Eric Anholt2015-06-201-1/+5
* ilo: clean up header includesChia-I Wu2015-06-205-2/+5
* ilo: avoid ilo_ib_state in genX_3DPRIMITIVE()Chia-I Wu2015-06-202-10/+8
* ilo: move gen6_so_SURFACE_STATE() out of coreChia-I Wu2015-06-202-52/+53
* ilo: add ilo_state_sol_bufferChia-I Wu2015-06-206-103/+317
* ilo: add ilo_state_index_bufferChia-I Wu2015-06-207-70/+171
* ilo: add ilo_state_vertex_bufferChia-I Wu2015-06-207-54/+189
* ilo: add 3DSTATE_VF_INSTANCING to ilo_state_vfChia-I Wu2015-06-209-67/+168
* ilo: add 3DSTATE_VF to ilo_state_vfChia-I Wu2015-06-209-66/+190
* ilo: embed pipe_index_buffer in ilo_ib_stateChia-I Wu2015-06-203-45/+40
* ilo: fix a buffer overrunChia-I Wu2015-06-201-1/+1
* ilo: fix a -Wmaybe-uninitialized warningChia-I Wu2015-06-201-0/+1
* llvmpipe: Truncate the binned constants to max const buffer size.Jose Fonseca2015-06-191-1/+4
* ilo: remove missing ilo_fence.h from the sources listEmil Velikov2015-06-181-1/+0
* vc4: Move tile state/alloc allocation into the kernel.Eric Anholt2015-06-179-101/+72
* vc4: Move RCL generation into the kernel.Eric Anholt2015-06-1711-676/+725
* vc4: Add dumping of VC4_PACKET_TILE_BINNING_MODE_CONFIG.Eric Anholt2015-06-171-1/+32
* vc4: Fix memory leak from simple_list conversion.Eric Anholt2015-06-171-3/+2
* vc4: Track the number of BOs allocated and their size.Eric Anholt2015-06-172-7/+100
* nvc0/ir: can't have a join on a load with an indirect sourceIlia Mirkin2015-06-171-1/+1
* vc4: Make sure that direct texture clamps have a minimum value of 0.Eric Anholt2015-06-162-25/+66
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