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* r600g: atomize sampler state v2Jerome Glisse2012-08-067-452/+262
| | | | | | | | | | | Use atom for sampler state. Does not provide new functionality or fix any bug. Just a step toward full atom base r600g. v2: Split seamless on r6xx/r7xx into it's own atom. Make sure it's emited after sampler and with a pipeline flush before otherwise it does not take effect. Signed-off-by: Jerome Glisse <[email protected]>
* llvmpipe: consolidate the sampler and sampler view setting codeBrian Paul2012-08-061-68/+56
| | | | | | | | Less code. And as with softpipe, if/when we consolidate the pipe_context functions for binding sampler state, this will make the llvmpipe changes trivial. Reviewed-by: José Fonseca <[email protected]>
* llvmpipe: combine vertex/fragment sampler state into an arrayBrian Paul2012-08-068-42/+41
| | | | | | This will allow code consolidation in the next patch. Reviewed-by: José Fonseca <[email protected]>
* softpipe: consolidate vert/frag/geom sampler setting functionsBrian Paul2012-08-061-112/+54
| | | | | | | | | | | | The functions for setting samplers and sampler views for vertex, fragment and geometry shaders were nearly identical. Now they use shared code. In the future, if the pipe_context functions for setting samplers and sampler views for vert/frag/geom/compute are combined, this will make updating the softpipe driver a snap. Reviewed-by: José Fonseca <[email protected]>
* softpipe: consolidate sampler-related arraysBrian Paul2012-08-066-121/+99
| | | | | | | | | | Combine separate arrays for vertex/fragment/geometry samplers, etc into one array indexed by PIPE_SHADER_x. This allows us to collapse separate code for vertex/fragment/geometry state into loops over the shader stage. More to come. Reviewed-by: José Fonseca <[email protected]>
* softpipe: combine vert/frag/geom texture caches in an arrayBrian Paul2012-08-065-91/+60
| | | | | | This lets us consolidate some code now, and more in subsequent patches. Reviewed-by: José Fonseca <[email protected]>
* i915g: silence a const pointer warningBrian Paul2012-08-041-1/+1
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* radeonsi: fix build failure after blitter changesMarek Olšák2012-08-041-1/+1
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* r600g: precompute color buffer state in pipe_surface and reuse itMarek Olšák2012-08-045-130/+175
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* r600g: precompute depth buffer state in pipe_surface and reuse itMarek Olšák2012-08-043-77/+92
| | | | | This is done on-demand, because we don't know in advance if a zbuffer will be bound as depth or color.
* r600g: simplify create_surfaceMarek Olšák2012-08-041-20/+8
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* r600g: drop the old texture allocation codeMarek Olšák2012-08-047-691/+233
| | | | Made obsolete by the libdrm surface allocator.
* r600g: make sure copying of all texture formats is acceleratedMarek Olšák2012-08-042-52/+54
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* gallium/u_blitter: add a query for checking whether copying is supportedMarek Olšák2012-08-042-5/+9
| | | | v2: add comments
* r600g: don't decompress depth or stencil if there isn't anyMarek Olšák2012-08-044-9/+17
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* r600g: correct texture memory size for Z32F_S8X24 on evergreenMarek Olšák2012-08-041-7/+16
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* gallium/u_blitter: remove fallback for stencil copy that all drivers skippedMarek Olšák2012-08-042-2/+2
| | | | Reviewed-by: Brian Paul <[email protected]>
* gallium/u_blitter: add ability to blit only depth or only stencilMarek Olšák2012-08-041-1/+1
| | | | Reviewed-by: Brian Paul <[email protected]>
* r600g: fix F2U opcode translationDave Airlie2012-08-041-1/+1
| | | | Signed-off-by: Marek Olšák <[email protected]>
* radeon/llvm: Add $(LLVM_LDFLAGS) to the loader linker flagsTom Stellard2012-08-021-1/+1
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* radeon/llvm: Add support for more f32 CMP instructions on SITom Stellard2012-08-021-5/+15
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* radeon/llvm: Add support for fneg on SITom Stellard2012-08-022-0/+16
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* radeon/llvm: Add support for fp_to_sint on SITom Stellard2012-08-021-1/+3
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* radeon/llvm: Remove CMOVLOG DAG nodeTom Stellard2012-08-026-75/+9
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* radeonsi: Properly initialize si_shader_ctx.radeon_bldTom Stellard2012-08-021-0/+1
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* radeonsi: Handle TGSI TXP opcode.Michel Dänzer2012-08-021-2/+24
| | | | | Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeonsi: Handle TGSI DIV opcode.Michel Dänzer2012-08-021-0/+5
| | | | | Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* svga: remove questionable INLINE qualifiersBrian Paul2012-08-021-2/+2
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* svga: sort #includesBrian Paul2012-08-021-4/+4
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* svga: add some comments in svga_screen_cache.cBrian Paul2012-08-021-1/+14
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* svga: whitespace, formatting fixesBrian Paul2012-08-021-52/+54
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* svga: remove unneeded 'struct svga_screen' declarationsBrian Paul2012-08-022-2/+0
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* radeon/llvm: fix fp immediates on SIChristian König2012-08-021-7/+20
| | | | | | | | I don't know if this is a good idea, but it fixes the problem at hand. Signed-off-by: Christian König <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeonsi: fix TEX writemaskChristian König2012-08-021-2/+2
| | | | | | | | | Using the writemask in the sampler results in packet VGPRS. For now just sample all components and let llvm chose the right one. Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: fix shader param and color countChristian König2012-08-021-5/+6
| | | | | Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: fix texture loads from sampler > 0Christian König2012-08-021-2/+2
| | | | | | | | | The backend is multiplying the offset by the numbers of elements anyway, so doing it twice just makes everything crash. Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: disable tiling until we fixed all bugsChristian König2012-08-021-0/+2
| | | | | | | Currently there are more important things to worry about. Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* nv50,nvc0: make resolve sampler objects allow sRGB conversionChristoph Bumiller2012-08-013-12/+25
| | | | | | | Just figured out what that bit does. Note: It's converted back to sRGB on write, so no effective conversion occurs.
* Revert "gallium: specify resource_resolve destination via a pipe_surface"Christoph Bumiller2012-08-014-31/+45
| | | | | | | | | | | This reverts commit 5d5af7d359e0060fa00b90a8f04900b96f9058b0. It turns out the issue this was supposed to fix merely counter-acted a bug in the hardware driver that I wasn't aware of. The resource_resolve is not supposed to do sRGB conversion, period. (This would violate the requirement that source and destination must be of the same format).
* radeon/llvm: fix calculation of max register numberChristian König2012-08-011-1/+1
| | | | | Signed-off-by: Christian König <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: Add pseudo-support for 64-bit immediate types on SITom Stellard2012-07-312-0/+23
| | | | | | | | SI does not support 64-bit immediates natively, but llvm will generate i64 immediates when indexing loads and stores (since SI has 64-bit pointers). The i64 indices will always be small enough to fit into 32-bits (i.e. the high 32 bits will always be all zeros), so we can treat these index values as 32-bits.
* radeon/llvm: Fix incorrect return value in SelectADDRReg()Tom Stellard2012-07-311-1/+1
| | | | We need to return true when we match the pattern.
* radeon/llvm: Move SMRD IMM pattern before SMRD SGPR patternTom Stellard2012-07-311-7/+6
| | | | | | | In tablegen, if two patterns match, the one that comes first in the file is given preference. We want the SMRD IMM pattern to be given preference, because it encodes the pointer offset in its immediate field, which saves us an add instruction.
* radeon/llvm: Cleanup AMDIL.hTom Stellard2012-07-304-91/+26
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* radeon/llvm: Rename all AMDIL* classes to AMDGPU*Tom Stellard2012-07-3030-496/+496
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* radeon/llvm: Merge AMDILSubtarget into AMDGPUSubtargetTom Stellard2012-07-3025-324/+156
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* radeon/llvm: Merge AMDILTargetLowering class into AMDGPUTargetLoweringTom Stellard2012-07-3011-241/+144
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* radeon/llvm: Remove IL_cmp DAG nodeTom Stellard2012-07-304-502/+2
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* radeon/llvm: Cleanup and reorganize AMDIL .td filesTom Stellard2012-07-3013-2303/+335
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* radeon/llvm: Remove lowering code for unsupported featuresTom Stellard2012-07-308-805/+50
| | | | e.g. function calls, load/store from stack
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