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* r600g,radeonsi: Assert that there's enough space after flushingMichel Dänzer2015-06-081-3/+2
| | | | | Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600g: fix a coverity defect in streamout codeMarek Olšák2015-06-051-1/+1
| | | | Reported by Ilia Mirkin.
* tgsi/ureg: don't emit in/out arrays if drivers don't support ranged declarationsMarek Olšák2015-06-0510-0/+13
| | | | | | Softpipe, llvmpipe, r300g, and radeonsi pass tests. Other drivers need testing. Freedreno and nv30 are definitely broken. Other drivers seem to be alright.
* llvmpipe: Implement stencil exportRoland Scheidegger2015-06-044-15/+21
| | | | | | | | | | | | | Pretty trivial, fixes the issue that we're expected to be able to blit stencil surfaces (as the blit just relies on util blitter code which needs stencil export to do it). 2 piglits skip->pass, 11 fail->pass v2: prettify, keep different stencil ref value handling out of depth/stencil test itself. Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* vc4: Don't bother with safe list traversal in CSE.Eric Anholt2015-05-291-1/+1
| | | | We don't remove or move instructions.
* vc4: Convert from simple_list.h to list.hEric Anholt2015-05-2919-139/+87
| | | | list.h is a nicer and more familiar set of list functions/macros.
* vc4: Make sure we allocate idle BOs from the cache.Eric Anholt2015-05-291-1/+11
| | | | | | | | | | | | | We were returning the most recently freed BO, without checking if it was idle yet. This meant that we generally stalled immediately on the previous frame when generating a new one. Instead, allocate new BOs when the *oldest* BO is still busy, so that the cache scales with how much is needed to keep some frames outstanding, as originally intended. Note that if you don't have some throttling happening, this means that you can accidentally run the system out of memory. The kernel is now applying some throttling on all execs, to hopefully avoid this.
* vc4: Fix return value handling for BO waits.Eric Anholt2015-05-291-12/+15
| | | | | If the wait ever returned -ETIME, we'd abort because the errno was stored in errno and not drmIoctl()'s return value.
* radeon/llvm: reset temps_count on deallocationMarek Olšák2015-05-291-0/+1
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeon/llvm: don't use a static array size for radeon_llvm_context::arrays (v2)Marek Olšák2015-05-292-7/+12
| | | | | | v2: - don't use realloc (tgsi_shader_info provides the size) Reviewed-by: Michel Dänzer <[email protected]>
* softpipe: fix offset wrapping calculations (v2)Dave Airlie2015-05-291-78/+68
| | | | | | | | | | | | | | | Roland pointed out my previous attempt was lacking, so I enhanced the texwrap piglit test, and tested them. This fixes the offset calculations in a number of areas by adding the offset first, it also fixes the fastpaths, which I forgot to address in the previous commit. v2: try and avoid divides in most paths, the repeat mirror path really was ugly no matter which way I went, so I left it having the divide. Also fix the gather lod calculation bug. Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* vc4: Just stream out fallback IB contents.Eric Anholt2015-05-276-42/+41
| | | | | | | | | | | | | | | The idea I had when I wrote the original shadow code was that you'd see a set_index_buffer to the IB, then a bunch of draws out of it. What's actually happening in openarena is that set_index_buffer occurs at every draw, so we end up making a new shadow BO every time, and converting more of the BO than is actually used in the draw. While I could maybe come up with a better caching scheme, for now just do the simple thing that doesn't result in a new shadow IB allocation per draw. Improves performance of isosurf in drawelements mode by 58.7967% +/- 3.86152% (n=8).
* vc4: Don't try to put our dmabuf-exported BOs into the BO cache.Eric Anholt2015-05-271-0/+1
| | | | | | | We'd sometimes try to reallocate something that X was using as a new pipe_resource, and potentially conflict in our rendering. But even worse, if we reallocated the BO as a shader, the kernel would reject rendering using the shader.
* vc4: Don't forget to make our raster shadow textures non-raster.Eric Anholt2015-05-271-0/+3
| | | | | | Not sure what happened in my testing that made the previous shadow code fix glxgears swapbuffering, but this also fixes lots of CopyArea in X (like dragging xlogo around in metacity).
* vc4: make vc4_begin_query() return a booleanSamuel Pitoiset2015-05-271-1/+2
| | | | | | | | I forgot to make the change in 96f164f6f047833091eb98a73aa80c31dc94f962. This fixes a warning with GCC and probably an error with Clang. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* radeonsi: use a switch statement in si_delete_shader_selectorMarek Olšák2015-05-261-6/+13
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: use a switch statement in si_shader_selector_keyMarek Olšák2015-05-261-9/+16
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: fix scratch buffer setup for geometry shadersMarek Olšák2015-05-261-2/+9
| | | | | Cc: 10.6 <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: remove unused cases from si_shader_io_get_unique_indexMarek Olšák2015-05-261-14/+3
| | | | | | | These can't occur between VS and GS, because GS is only supported in the core profile. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: don't count special outputs for the VS export countMarek Olšák2015-05-261-0/+5
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: add support for PIPE_CAP_TGSI_TEXCOORDMarek Olšák2015-05-264-15/+13
| | | | | | | | | | | | | Without it, texcoords are mapped to GENERIC[0..7], PointCoord is mapped to GENERIC[8], and user-defined varyings start from GENERIC[9]. Since texcoords can only be used between VS and PS, and PointCoord is PS-only, it's silly to always start from GENERIC[9] in all other shaders (such as LS, HS, ES, GS). This adds support for TEXCOORD and PCOORD semantics. As a result, st/mesa will use GENERIC[0] as a base for user-defined varyings, which should make linking ES and GS as well as tessellation shaders at runtime easier. Reviewed-by: Michel Dänzer <[email protected]>
* gallium: use const in set_tess_stateMarek Olšák2015-05-261-2/+2
| | | | Reviewed-by: Ilia Mirkin <[email protected]>
* nv30: falling back to draw path for edgeflag does no goodIlia Mirkin2015-05-251-3/+2
| | | | | | | | | The problem is that the EDGEFLAG has to be toggled at vertex submission time. This can be done from either the draw or the regular paths. Avoid falling back to draw just because there's an edgeflag. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.5 10.6" <[email protected]>
* nv30/draw: switch varying hookup logic to know about texcoordsIlia Mirkin2015-05-251-9/+16
| | | | | | | | | | | | Commit 8acaf862dfe switched things over to use TEXCOORD instead of GENERIC, but did not update the nv30 swtnl draw paths. This teaches the draw logic about TEXCOORD. Among other things, this fixes a crash in demos/arbocclude when using swtnl. Curiously enough, the point-sprite piglit works without this. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.5 10.6" <[email protected]>
* nv30/draw: allocate vertex buffers in gartIlia Mirkin2015-05-251-6/+10
| | | | | | | | | | These are only used once per draw, so it makes sense to keep them in GART. Also take this opportunity to modernize the buffer mapping API usage. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Ben Skeggs <[email protected]> Cc: "10.5 10.6" <[email protected]>
* nv30/draw: only use the DMA1 object (GART) if the bo is not in VRAMIlia Mirkin2015-05-251-3/+3
| | | | | | | | | Instead of always having it in the data, let the bo placement decide it. This fixes glxgears with swtnl forced on. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Ben Skeggs <[email protected]> Cc: "10.5 10.6" <[email protected]>
* nv30/draw: fix indexed draws with swtnl path and a resource index bufferIlia Mirkin2015-05-251-3/+3
| | | | | | | The map = assignment was missing. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.5 10.6" <[email protected]>
* llvmpipe: (trivial) add parantheses in (!x == y) expressionRoland Scheidegger2015-05-251-1/+1
| | | | | | | Apparently some compilers think we probably wanted to do !(x == y) instead and issue a warning, so just shut it up... No functional change, obviously. Cc: <[email protected]>
* nv30/draw: draw expects constbuf size in bytes, not vec4 unitsIlia Mirkin2015-05-251-1/+1
| | | | | | | | This fixes glxgears with NV30_SWTNL=1 forced on. Probably fixes a bunch of other situations where we fall back to the swtnl path. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.5 10.6" <[email protected]>
* nv30/draw: avoid leaving stale pointers in draw stateIlia Mirkin2015-05-251-4/+4
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.5 10.6" <[email protected]>
* nv30: fix clip plane uploads and enable changesIlia Mirkin2015-05-241-9/+7
| | | | | | | | | | | | nv30_validate_clip depends on the rasterizer state. Also we should upload all the new clip planes on change since next time the plane data won't have changed, but the enables might. This fixes fixed-clip-enables and vs-clip-vertex-enables shader tests. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Tobias Klausmann <[email protected]> Cc: "10.5 10.6" <[email protected]>
* nv30: avoid doing extra work on clear and hitting unexpected statesIlia Mirkin2015-05-245-9/+11
| | | | | | | | | | | | Clearing can happen at a time when various state objects are incoherent and not ready for a draw. Some of the validation functions don't handle this well, so only flush the framebuffer state. This has the advantage of also not doing extra work. This works around some crashes that can happen when clearing. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Tobias Klausmann <[email protected]>
* nv30: avoid leaking render state and draw shadersIlia Mirkin2015-05-243-0/+16
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.5 10.6" <[email protected]>
* nv30: don't leak fragprog constsIlia Mirkin2015-05-241-0/+1
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.5 10.6" <[email protected]>
* nv50/ir: avoid messing up arg1 of PFETCHIlia Mirkin2015-05-231-2/+18
| | | | | | | | | | | | | | There can be scenarios where the "indirect" arg of a PFETCH becomes known, and so the code will attempt to propagate it. Use this opportunity to just fold it into the first argument, and prevent the load propagation pass from touching PFETCH further. This fixes gs-input-array-vec4-index-rd.shader_test and vs-output-array-vec4-index-wr-before-gs.shader_test on nvc0 at least. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Tobias Klausmann <[email protected]> Cc: "10.5 10.6" <[email protected]>
* nv30: check nouveau_bo_map output of notify boIlia Mirkin2015-05-231-1/+1
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: a geometry shader can have up to 1024 vertices outputIlia Mirkin2015-05-231-1/+1
| | | | | | | | The 1024 is already reported everywhere, not sure where this 0x1ff came from. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.5 10.6" <[email protected]>
* nv50: fix PIPE_QUERY_TIMESTAMP_DISJOINT, based on nvc0Samuel Pitoiset2015-05-231-17/+22
| | | | | | | | | PIPE_QUERY_TIMESTAMP_DISJOINT could not work because q->ready was always set to FALSE. To fix this issue, add more different states for queries according to nvc0. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0/ir: LOAD's can't be used for shader inputsIlia Mirkin2015-05-222-0/+2
| | | | | | | | | | We forgot to convert to VFETCH in case of indirect access. Fix that. This avoids crashes on the new gs-input-array-vec4-index-rd and vs-output-array-vec4-index-wr-before-gs but they still fail. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.5 10.6" <[email protected]>
* nv50/ir: guess that the constant offset is the starting slot of arrayIlia Mirkin2015-05-221-2/+4
| | | | | | | | When we get something like IN[ADDR[0].x+5], we will now guess that we should look at IN[5] for the "base" information. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.5 10.6" <[email protected]>
* nvc0/ir: set ftz when sources are floats, not just destinationsIlia Mirkin2015-05-221-3/+2
| | | | | | | | In the case of a compare, the destination might be a predicate, but we still want to flush denorms. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.5 10.6" <[email protected]>
* nv50/ir: allow OP_SET to merge with OP_SET_AND/etc as well as a negIlia Mirkin2015-05-221-26/+55
| | | | | | | | | | | | | | | | | | | | This covers the pattern where a KILL_IF is used, which triggers a comparison of -x to 0. This can usually be folded into the comparison whose result is being compared to 0, however it may, itself, have already been combined with another comparison. That shouldn't impact the logic of this pass however. With this and the & 1.0 change, code like 00000020: 001c0001 80081df4 set b32 $r0 lt f32 $r0 0x3e800000 00000028: 001c0000 201fc000 and b32 $r0 $r0 0x3f800000 00000030: 7f9c001e dd885c00 set $p0 0x1 lt f32 neg $r0 0x0 00000038: 0000003c 19800000 $p0 discard becomes 00000020: 001c001d b5881df4 set $p0 0x1 lt f32 $r0 0x3e800000 00000028: 0000003c 19800000 $p0 discard Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: optimize set & 1.0 to produce boolean-float setsIlia Mirkin2015-05-222-0/+29
| | | | | | | | This has started to happen more now that the backend is producing KILL_IF more often. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Tobias Klausmann <[email protected]>
* nvc0/ir: allow iset to produce a boolean floatIlia Mirkin2015-05-223-5/+16
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: avoid jumping to a sched instructionIlia Mirkin2015-05-223-2/+9
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nv50: fix PIPELINE_STATISTICS with HUD, based on nvc0Samuel Pitoiset2015-05-221-1/+2
| | | | | | | Tested on NVA8. No regression for ARB_pipeline_statistics piglit tests. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50: fix 64-bit queries with HUD, based on nvc0Samuel Pitoiset2015-05-221-1/+13
| | | | | | | | | A sequence number is written for 32-bits queries to make sure they are ready, but not for 64-bits queries. Instead, we have to use a fence in order to fix the HUD because it doesn't wait until the result is ready. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* radeon/vce: adapt new firmware interface changesChristian König2015-05-224-2/+252
| | | | | | | | | v2: make this also compatible with original released firmware v3 (chk): switch to original idea of separate files for fw versions Signed-off-by: Leo Liu <[email protected]> Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> (v2)
* radeon/vce: move CPB handling function into common codeChristian König2015-05-223-29/+48
| | | | | | They are not firmware version dependent. Signed-off-by: Christian König <[email protected]>
* freedreno/a3xx: set .zw of sprite coords to .01Ilia Mirkin2015-05-201-3/+6
| | | | | | | | Fixes non-determinism in bin/point-sprite rendering, and the stars on the intro screen to neverball. Cc: "10.6" <[email protected]> Signed-off-by: Ilia Mirkin <[email protected]>
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