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* radeon/llvm: Use tablegen pattern to lower bitconvertTom Stellard2012-05-254-294/+11
* radeon/llvm: Use a custom inserter to lower FNEGTom Stellard2012-05-255-22/+15
* radeon/llvm: Use a custom inserter to lower CLAMPTom Stellard2012-05-259-84/+41
* radeon/llvm: Use a custom inserter to lower FABSTom Stellard2012-05-2510-42/+41
* r600g: handle R16G16B16_FLOAT and R32G32B32_FLOAT in translate_colorswapKai Wasserbäch2012-05-251-0/+2
* svga: remove the special zero-stride vertex array codeBrian Paul2012-05-259-153/+12
* Revert "r600g: set round_mode to truncate and get rid of tgsi_f2i on evergreen"Vadim Girlin2012-05-252-6/+56
* radeon/llvm: add FLT_TO_UINT, UINT_TO_FLT instructionsVadim Girlin2012-05-251-0/+20
* radeon/llvm: prepare to revert the round mode state to defaultVadim Girlin2012-05-251-2/+9
* radeon/llvm: fix sampler index in llvm_emit_texVadim Girlin2012-05-251-2/+4
* radeon/llvm: fix opcode for RECIP_UINT_r600Vadim Girlin2012-05-251-1/+1
* radeon/llvm/loader: convert hardcoded gpu name to optionVadim Girlin2012-05-251-2/+3
* r600g: add RECIP_INT, PRED_SETE_INT to r600_bytecode_get_num_operandsVadim Girlin2012-05-251-0/+2
* i915g: Check for geometry shader earlier in i915_set_constant_buffer.Vinson Lee2012-05-241-4/+4
* radeon/llvm: Lower UDIV using the Selection DAGTom Stellard2012-05-248-212/+126
* radeon/llvm: Remove auto-generated AMDIL->ISA conversion codeTom Stellard2012-05-2414-280/+28
* radeon/llvm: Remove AMDIL instructions MULHI, SMULTom Stellard2012-05-243-10/+5
* radeon/llvm: Remove AMDIL bitshift instructions (SHL, SHR, USHR)Tom Stellard2012-05-248-693/+6
* radeon/llvm: Remove AMDIL FTOI and ITOF instructionsTom Stellard2012-05-247-316/+7
* radeon/llvm: Remove AMDIL EXP* instructionsTom Stellard2012-05-245-15/+7
* radeon/llvm: Remove AMDIL ADD instructionsTom Stellard2012-05-246-179/+4
* radeon/llvm: Remove AMDIL binary instrutions (OR, AND, XOR, NOT)Tom Stellard2012-05-248-422/+8
* radeon/llvm: Remove AMDILMachinePeephole passTom Stellard2012-05-244-177/+0
* radeon/llvm: Remove AMDIL CMP instructions and associated lowering codeTom Stellard2012-05-243-661/+22
* radeon/llvm: Remove AMDIL ROUND_NEAREST instructionTom Stellard2012-05-244-6/+6
* radeon/llvm: Remove AMDIL ROUND_POSINF instructionTom Stellard2012-05-244-6/+10
* radeon/llvm: Add custom SDNode for FRACTTom Stellard2012-05-246-6/+10
* radeon/llvm: Use -1 as true value for SET* integer instructionsTom Stellard2012-05-243-32/+28
* radeon/llvm: Handle SETGE_INT, SETGE_UINT, and SETGT_UINT opcodesTom Stellard2012-05-241-0/+6
* radeon/llvm: Avoid error with SI in EmitInstrWithCustomInserter()Tom Stellard2012-05-241-0/+1
* llvmpipe: Fix alpha testing precision on rgba8 formats.José Fonseca2012-05-223-1/+34
* nv30: check for NULL vertex buffers in prevalidate_vbufsChristoph Bumiller2012-05-221-1/+1
* nv50: make unaligned index buffer offsets work againChristoph Bumiller2012-05-221-1/+3
* nvc0: don't set NEW_IDXBUF in nvc0_switch_pipe_context if none is boundChristoph Bumiller2012-05-221-0/+2
* llvmpipe: Added a error counter to lp_test_conv.James Benton2012-05-211-3/+7
* llvmpipe: Changed known failures in lp_test_conv.James Benton2012-05-211-3/+9
* llvmpipe: Added fixed point types tests to lp_test_conv.James Benton2012-05-211-6/+7
* radeon/llvm: Handle selectcc DAG nodeTom Stellard2012-05-207-54/+350
* svga: whitespace, comments, formatting clean-upsBrian Paul2012-05-191-38/+31
* svga: return PIPE_OK instead of 0Brian Paul2012-05-195-11/+11
* svga: fix zero-stride vertex array bugBrian Paul2012-05-191-2/+6
* radeonsi: Only honour point related rasterizer state when rendering points.Michel Dänzer2012-05-181-2/+3
* radeonsi: Fix parameter cache offsets for fragment shader inputs.Michel Dänzer2012-05-183-2/+4
* radeon/llvm: Fix segfault while lowering lrp intrinsicTom Stellard2012-05-171-2/+3
* radeon/llvm: Add DAG nodes for MIN instructionsTom Stellard2012-05-176-14/+38
* llvmpipe: Avoid adding floating point zero to flat inputs.José Fonseca2012-05-181-1/+4
* llvmpipe: Implement TXQ.Olivier Galibert2012-05-181-0/+23
* llvmpipe: Don't mess with the provoking vertex when inverting a triangle.Olivier Galibert2012-05-181-5/+40
* radeon/llvm: Lower lrp intrinsic during ISelTom Stellard2012-05-173-7/+19
* radeon/llvm: Remove AMDIL MAD instruction defsTom Stellard2012-05-176-7/+14