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* nvc0: mark buffer texture range valid for shader imagesSamuel Pitoiset2016-06-033-0/+31
| | | | | | | | Loosely based on radeonsi (Thanks to Nicolai). Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Cc: 12.0 <[email protected]>
* svga: allow copy box in svga_transfer_dma_band()Charmaine Lee2016-06-021-13/+20
| | | | | | | | | | | | | Instead of just allow copy of a rectangle in svga_transfer_dma_band(), this patch allows it to copy a box, hence allows copy a 3d texture in one transfer. Fixes black screen in running Heaven after commit fb9fe35. (Bug 1663282) Tested with Heaven, glretrace, piglit. Reviewed-by: Sinclair Yeh <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* freedreno: fix bad bitshift warningsRob Clark2016-06-021-0/+2
| | | | | | | | | | | | | Coverity doesn't realize idx will never be negative. Throw in some assert()s to help it out. (Hopefully assert() isn't getting compiled out for coverity build.. but there seems to be just one way to find out. We might have to change these to assume()) Fixes CID 1362442, 1362443 Signed-off-by: Rob Clark <[email protected]>
* freedreno: assume builtin shaders do compileRob Clark2016-06-021-1/+2
| | | | | | | | | | Maybe we should switch to ureg to build the builtin shaders. But at any rate, if they fail to compile it is because someone messed them up (or changed TGSI syntax?). CID 1362444 Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: silence coverity warningRob Clark2016-06-021-0/+6
| | | | | | CID 1362451 Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx+a4xx: fix potential null ptr derefRob Clark2016-06-022-2/+4
| | | | | | | | Coverity spotted the a3xx case (not sure why not the a4xx). CID 1362452 Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix coverity warningRob Clark2016-06-021-1/+3
| | | | | | CID 1362453 Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: use nir_shader_get_entrypoint() helperRob Clark2016-06-021-10/+1
| | | | | | Should also fix coverity warning: CID 1362454 Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: fix incorrect enum typeRob Clark2016-06-021-1/+1
| | | | | | | | a4xx has it's own enum, different from a2xx/a3xx. Spotted by coverity: CID 1362458, 1362459 Signed-off-by: Rob Clark <[email protected]>
* freedreno: fix coverity negative array index warningRob Clark2016-06-021-0/+2
| | | | | | | | | | Never can happen, since query would not have been created in the first place if pidx(query_type) return negative. Lets let coverity realize this. CID 1362460 Signed-off-by: Rob Clark <[email protected]>
* freedreno: fix dereference before null checkRob Clark2016-06-021-2/+1
| | | | | | | | | | ptr can actually never be null so just drop the check. CID 1362464 (#1 of 1): Dereference before null check (REVERSE_INULL) check_after_deref: Null-checking ptr suggests that it may be null, but it has already been dereferenced on all paths leading to the check. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: only update/emit bordercolor state when neededRob Clark2016-06-023-17/+27
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: only update/emit bordercolor state when neededRob Clark2016-06-023-17/+26
| | | | | | I noticed in stk that it was contributing to a lot of overhead. Signed-off-by: Rob Clark <[email protected]>
* radeon/uvd: fix the H264 level for Tonga v2Christian König2016-06-021-1/+1
| | | | | | | | | | We support 5.2 for a while now. v2: we even support 5.2 for H264, 5.1 is for HEVC. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Cc: <[email protected]>
* radeon/winsys: introduce radeon_winsys_cs_chunkNicolai Hähnle2016-06-019-34/+52
| | | | | | | We will chain multiple chunks together and will keep pointers to the older chunks to support IB dumping. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/sid: add packet definitions for IB chainingNicolai Hähnle2016-06-012-0/+15
| | | | | | While we're at it, add packet printing in si_debug. Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: use cs_check_space throughoutNicolai Hähnle2016-06-015-10/+7
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeon/winsys: add cs_check_spaceNicolai Hähnle2016-06-011-0/+9
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: set correct stencil tile mode for texturingMarek Olšák2016-06-011-2/+8
| | | | | | Sadly, this doesn't affect SI and VI in any way. Reviewed-by: Michel Dänzer <[email protected]>
* gallium/radeon: lower memory usage during texture transfersMarek Olšák2016-06-012-4/+29
| | | | | | | | | | | | This improves throughput by keeping TTM overhead down. Some piglit tests such as texelFetch and streaming-texture-leak will use less memory now. v2: use gart_size / 4 as the threshold Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: invalidate busy linear textures for whole-texture uploadsMarek Olšák2016-06-011-2/+28
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* gallium/radeon: degrade tiled textures mapped often to linearMarek Olšák2016-06-012-0/+103
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* gallium/radeon: clean up and better comment use_staging_textureMarek Olšák2016-06-011-19/+23
| | | | | | | Next commits will add other things around this. Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi: set some colorbuffer register fields at emit timeMarek Olšák2016-06-013-50/+47
| | | | | | | to allow reallocating the texture storage with different parameters Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi: implement global resetting of texture descriptorsMarek Olšák2016-06-014-6/+64
| | | | | | | it will be used by texture reallocation Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi: move code for setting one shader image into separate functionMarek Olšák2016-06-011-71/+82
| | | | | | | v2: fix set_shader_images(..., NULL). Found by Christoph Haag. Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi: set some image descriptor fields at bind timeMarek Olšák2016-06-014-71/+111
| | | | | | | | mainly the fields that can change by reallocating a texture and changing the tile mode Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* gallium/radeon: strenghten some checking for DMA preparationMarek Olšák2016-06-011-1/+6
| | | | | | | | | | Just for consistency. This doesn't fix anything, because DCC is not supported with non-mipmapped textures. v1.1: fix the comment about DCC Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* gallium/util: add util_texrange_covers_whole_level from radeonMarek Olšák2016-06-011-17/+6
| | | | | | Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi: fix the raster config setup for 1 RB iceland chipsAlex Deucher2016-06-011-1/+4
| | | | | | | | | I didn't realize there were 1 and 2 RB variants when this code was originally added. Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: 11.1 11.2 12.0 <[email protected]>
* nv50/ir: fix error finding free element in bitset in some situationsIlia Mirkin2016-05-311-0/+6
| | | | | | | | | | | | | | This really only hits for bitsets with a size of a multiple of 32. We can end up with pos = -1 as a result of the ffs, which we in turn decide is a valid position (since we fall through the loop and i == 1, we end up adding 32 to it, so end up returning 31 again). Up until recently this was largely unreachable, as the register file sizes were all 63 or 255. However with the advent of compute shaders which can restrict the number of registers, this can now happen. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "12.0" <[email protected]>
* nv50/ir: print relevant file's bitset when showing RA infoIlia Mirkin2016-05-311-4/+4
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* radeonsi: Decompress DCC textures in a render feedback loop.Bas Nieuwenhuizen2016-05-314-0/+113
| | | | | | | | | By using a counter to quickly reject textures that are not bound to a framebuffer, the performance impact when binding sampler_views/images is not too large. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Add counter to check if a texture is bound to a framebuffer.Bas Nieuwenhuizen2016-05-314-0/+26
| | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* vc4: Fix compiler warnings in fail_instr path of QIR validate passRhys Kidd2016-05-311-10/+10
| | | | | | | Introduced in 8e2d0843c02daf5280184f179ae8ed440ac90d7f. Signed-off-by: Rhys Kidd <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* svga: change enum pipe_resource_usage back to unsignedBrian Paul2016-05-311-1/+1
| | | | | | | | | This parameter is actually a bitmask of PIPE_TRANSFER_x flags. Change it back to a simple unsigned type. IIRC, some compilers complain about masks of enum values. Also, this make the function signature match u_resource_vtbl::transfer_map() again. Reviewed-by: Roland Scheidegger <[email protected]>
* radeonsi: fix CP DMA hazard with index buffer fetchesMarek Olšák2016-05-311-2/+20
| | | | Reviewed-by: Alex Deucher <[email protected]>
* r600g: do GL-compliant integer resolvesMarek Olšák2016-05-311-37/+1
| | | | | | | The GL spec has been clarified and the new rule says we should just copy 1 sample. u_blitter does the right thing. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: do GL-compliant integer resolvesMarek Olšák2016-05-311-37/+1
| | | | | | | The GL spec has been clarified and the new rule says we should just copy 1 sample. u_blitter does the right thing. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: don't flush TC at the end of IBs on DRM >= 3.2.0Marek Olšák2016-05-311-2/+3
| | | | | | It's not needed since it was fixed in the kernel. Reviewed-by: Alex Deucher <[email protected]>
* gallium/radeon: fixed division by zeroJakob Sinclair2016-05-311-0/+3
| | | | | | | | | | Coverity is getting a false positive that a division by zero can occur here. This change will silence the Coverity warnings as a division by zero cannot occur in this case. Signed-off-by: Jakob Sinclair <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* nvc0/ir: fix spilling predicates to registersIlia Mirkin2016-05-301-0/+4
| | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Cc: "11.1 11.2 12.0" <[email protected]>
* nvc0/ir: limit max number of regs based on availability in SMIlia Mirkin2016-05-302-2/+4
| | | | | | | | | This effectively limits registers to 32 and 64 for fermi and kepler when 1024 threads are used, but allows the full amount to be used with smaller thread sizes. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* nv50/ir: record number of threads in a compute shaderIlia Mirkin2016-05-305-2/+10
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* nv50/ir: Add missing handling of U64/S64 in inlinesPierre Moreau2016-05-301-1/+3
| | | | | Signed-off-by: Pierre Moreau <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* vc4: Fix doxygen warnings12.0-branchpointRhys Kidd2016-05-302-6/+6
| | | | | | | | Now that vc4 automated code documentation can be generated with doxygen, fix the warnings issued by Doxygen 1.8.11. Signed-off-by: Rhys Kidd <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* nvc0/ir: fix emission of predicate spill to registerIlia Mirkin2016-05-301-1/+2
| | | | | | The lane mask only applies to real mov's, while here we're using PSET. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: fix some compute texture validation bits on keplerIlia Mirkin2016-05-303-2/+7
| | | | | | | | | (a) Make sure to update the TIC in case of an updated buffer address (b) Mark newly-inactive textures dirty so that we update the handle in set_tex_handles. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* swr: automake: silence the python invocationEmil Velikov2016-05-301-7/+8
| | | | | Cc: Tim Rowley <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* swr: automake: attempt to fix the out-of-tree buildEmil Velikov2016-05-301-0/+7
| | | | | | | | | | Make sure that the output folder is created otherwise the python scripts yells at us. Cc: [email protected] Cc: Tim Rowley <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96238 Signed-off-by: Emil Velikov <[email protected]>
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