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* ilo: avoid brw_wm_barycentric_interp_mode in compilerChia-I Wu2014-04-141-17/+46
| | | | In preparation for genhw.
* ilo: add TOY_OPCODE_DOChia-I Wu2014-04-146-7/+10
| | | | | We used to give BRW_OPCODE_DO a special meaning, while we should have used TOY_OPCODE_DO.
* softpipe: fix shadow samplingHeinrich Janzing2014-04-111-68/+51
| | | | | | | | And remove nonsensical approximation of linear interpolation behavior for shadow samplers. Reviewed-by: Brian Paul <[email protected]> Tested-by: Brian Paul <[email protected]>
* softpipe: add PIPE_CAP_MIN/MAX_TEXTURE_GATHER_OFFSET query casesBrian Paul2014-04-111-0/+3
| | | | | | To silence compiler warnings. Reviewed-by: Ilia Mirkin <[email protected]>
* radeon/vce: implement B-frame supportChristian König2014-04-112-22/+53
| | | | | Signed-off-by: Slava Grigorev <[email protected]> Signed-off-by: Christian König <[email protected]>
* radeon/vce: add proper CPB backtrackChristian König2014-04-113-23/+123
| | | | | | Remember what frames we encoded at which position. Signed-off-by: Christian König <[email protected]>
* vl: add interface for H264 B-frame encodingChristian König2014-04-111-5/+6
| | | | Signed-off-by: Christian König <[email protected]>
* radeon/vce: remove RVCE_NUM_CPB_EXTRA_FRAMESChristian König2014-04-113-4/+2
| | | | | | Doesn't seems to be needed any more. Signed-off-by: Christian König <[email protected]>
* gallium: add a way to query min/max texture gather offsetsIlia Mirkin2014-04-1011-0/+24
| | | | | | | | Defaults to providing the same offsets as MIN/MAX_TEXEL_OFFSET. For nvc0, the offset can be -32/31. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* winsys/radeon: fix a race condition between winsys_create and winsys_destroyMarek Olšák2014-04-103-3/+3
| | | | | | | | | This also hides the reference count from drivers. v2: update the reference count while the mutex is locked in winsys_create Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Christian König <[email protected]>
* r600g: Don't leak bytecode on shader compile failureMichel Dänzer2014-04-101-7/+12
| | | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=74868 Cc: [email protected] Reviewed-by: Marek Olšák <[email protected]>
* freedreno/a3xx: assert() -> debug_assert()Rob Clark2014-04-091-1/+1
| | | | | | | | | We hit this assert with some piglit tests. Which appears to be a bug outside of freedreno. Previously we were relying on assert() being redefined to debug_assert() so that we didn't crash in release builds. Somehow that stopped working. So just use debug_assert() directly. Signed-off-by: Rob Clark <[email protected]>
* svga: move LIST_INITHEAD(dirty_buffers) earlier in svga_context_create()Brian Paul2014-04-091-2/+2
| | | | | | | | | | | | Fixes a crash in svga_context_flush_buffers() if we use the 'draw' module for AA lines (when the device doesn't support that feature). We need to initialize this list before we setup the swtnl pieces. Found/fixed by Charmaine Lee. Cc: "10.0" <[email protected]> Reviewed-by: Thomas Hellstrom <[email protected]> Reviewed-by: Jakob Bornecrantz <[email protected]>
* freedreno/a3xx/compiler: add CEILRob Clark2014-04-091-0/+1
| | | | | | fixes piglit glsl-fs-ceil Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx/compiler: fix neg mov'sRob Clark2014-04-091-20/+1
| | | | | | | | | | | | | | | | | | | | create_mov() was fixed up to handle neg/abs properly for interal mov's, using absneg.f, but forgot to fix it for TGSI MOV's. The problem with using add.f to handle negated mov's is that we can only take a single const reg src. So: MOV TEMP[n], -CONST[m] would turn into: add.f Rdst, (neg)CONST[m], 0.0 which would not work. Anyways, just remove the extra code and always use create_mov() which DTRT. This fixes piglit vs-op-neg-int test. Signed-off-by: Rob Clark <[email protected]>
* radeonsi: allow fast color clear and Hyper-Z with 1D-tiled surfaces on CIKMarek Olšák2014-04-091-5/+5
| | | | This depends on my kernel fix. Hyper-Z is still disabled by default.
* r600g,radeonsi: add a bunch of useful queries for the HUDMarek Olšák2014-04-093-1/+41
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* r600g,radeonsi: set correct initial domain for shared resourcesMarek Olšák2014-04-091-1/+1
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* gallium/radeon: fix warningsMarek Olšák2014-04-092-1/+2
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* freedreno/a3xx: deal with optimized tex instructionsRob Clark2014-04-087-25/+41
| | | | | | | | | | | | | | | Keep track of whether we actually have any sam instructions in the resulting shader, rather than using TGSI SAMP declarations. If the sam instruction is optimized out, because the result is not used, we don't want to emit texture state, etc. In fact emitting sampler state and/or setting PIXLODENABLE bit when there are no texture fetches seems to cause lockup. In theory this should never happen for a "normal" shader, unless the state tracker is wonky. But it is a very real possibility for binning pass shaders. Signed-off-by: Rob Clark <[email protected]>
* svga: replace sampler assertion with conditionalBrian Paul2014-04-082-5/+33
| | | | | | | | | | | | | For TEX instructions, the set of samplers and sampler views should be consistent. The XA state tracker sometimes passes an inconsistent set of samplers and sampler views. Rather than assert and die, issue a warning. v2: add debugging code to detect inconsistent state. v3: also check for null sampler in svga_state_tss.c Cc: "10.0" "10.1" <[email protected]> Reviewed-by: Thomas Hellstrom <[email protected]>
* nouveau: fix firmware check on nvd7/nvd9Ilia Mirkin2014-04-071-3/+3
| | | | | | | | | | | | The kernel driver expects the class to be based on chipset generation rather than VP generation. Make sure to pass 90b1 for NVDX chipsets instead of 95b1. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77102 Fixes: 40dd777b33073 Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.1 10.0" <[email protected]> Reviewed-by: Maarten Lankhorst <[email protected]>
* nvc0: add support for texture gatherIlia Mirkin2014-04-074-5/+22
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: enable texture query lodIlia Mirkin2014-04-074-1/+55
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nv50: enable texture query lodIlia Mirkin2014-04-076-1/+34
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* gallium: add support for LODQ opcodes.Dave Airlie2014-04-0712-0/+12
| | | | | | | | | This opcode provide support for GL_ARB_texture_query_lod, Signed-off-by: Dave Airlie <[email protected]> [imirkin: rebase, docs update] Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* drivers/nouveau: mention dummy.cpp to use g++ linkerEmil Velikov2014-04-051-1/+1
| | | | | | | | | | The build system does not know that the static library is C++. Mention the cpp file to trigger generation of the proper variable and drop the hacky stdc++ linking. Cc: Ilia Mirkin <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* drivers/nouveau: use GALLIUM_COMMON_LIB_DEPSEmil Velikov2014-04-051-2/+1
| | | | | | Cc: Ilia Mirkin <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* drivers/r300: use GALLIUM_COMMON_LIB_DEPSEmil Velikov2014-04-051-1/+1
| | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76848 Tested-by: Vinson Lee <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* Revert "radeon: just don't map VRAM buffers at all"Leo Liu2014-04-041-2/+2
| | | | | | | | | This reverts commit 96e8b916a7a39a9ba58e92d1ad77b5501de63ac7. In the case of VCE encoding with raw YUV file, CPU load directly to VRAM is faster than combination of CPU writing to GTT and then blit to VRAM with GPU. Reviewed-by: Christian König <[email protected]>
* radeon/vce: cleanup cpb handlingLeo Liu2014-04-043-11/+38
| | | | | | | v2: fix whitespace errors, minor coding style changes Signed-off-by: Leo Liu <[email protected]> Signed-off-by: Christian König <[email protected]>
* llvmpipe: remove no-op checks in sampler, sampler_view functionsBrian Paul2014-04-031-14/+0
| | | | | Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: José Fonseca <[email protected]>
* softpipe: remove no-op checks in sampler, sampler_view functionsBrian Paul2014-04-031-14/+0
| | | | | Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: José Fonseca <[email protected]>
* svga: remove no-op checks in sampler, sampler_view functionsBrian Paul2014-04-031-15/+0
| | | | | | | | We are checking for no-ops in the CSO module for both of these items so there's no reason to do it in the driver. Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: José Fonseca <[email protected]>
* mesa/soft/llvmpipe: add fake MSAA supportDave Airlie2014-04-0211-0/+15
| | | | | | | | This adds a gallium cap that allows us to fake GL3.0 by not exposing MSAA on sw rendering. It also forces the extra extensions needed for GL3.2. Signed-off-by: Dave Airlie <[email protected]>
* nv50: implement clear_buffer to accelerate ARB_clear_buffer_objectIlia Mirkin2014-03-311-0/+115
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/a3xx/compiler: fix RECT texturesRob Clark2014-03-301-7/+24
| | | | | | | Whether or not the coords are normalized is handled in the texture state. But we otherwise need to treat RECT sample instructions as 2D. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx/compiler: avoid negative register idsRob Clark2014-03-301-2/+2
| | | | | | | | | | | In some cases, we need a register to be assigned up to three components before the base. Since we can't have negative register #'s, just shift everything up. May increase register usage for trivial shaders, but I don't think we are shader limited in those cases. A proper solution is going to require a better register assignment algorithm (which is on the TODO list), this is just a hack to get us by until then. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: missing wfiRob Clark2014-03-304-3/+20
| | | | | | | | | RB_FRAME_BUFFER_DIMENSION is not a banked context register, so we need to wait for the GPU to idle before updating it. But we'd rather not have unnecessary WFI's, so actually keep track if we need to emit it or not. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: little extra debugRob Clark2014-03-302-0/+5
| | | | | | Catch things which should not happen in debug builds. Signed-off-by: Rob Clark <[email protected]>
* freedreno: handle null samplerRob Clark2014-03-302-3/+8
| | | | | | | This is something that XA triggers. In some cases it will only use SAMP[1] (composite mask) but not SAMP[0] (composite src). Signed-off-by: Rob Clark <[email protected]>
* svga: add work-around for Sauerbraten Z fighting issueBrian Paul2014-03-263-2/+49
| | | | Reviewed-by: Jose Fonseca <[email protected]>
* svga: null out query's hwbuf pointer after destroyingBrian Paul2014-03-261-0/+1
| | | | | | Just to be extra safe. Reviewed-by: Jose Fonseca <[email protected]>
* svga: add some debug_printf() calls in the query object codeBrian Paul2014-03-261-2/+6
| | | | | | To help debug failures. Reviewed-by: Jose Fonseca <[email protected]>
* svga: fix a comment (sampler vs. sampler_view)Brian Paul2014-03-261-1/+1
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* llvmpipe: Fix llvmpipe_create_gs_state.Zack Rusin2014-03-261-3/+5
| | | | | | | Revert unintended behaviour change from commit b995a010e688bc4d4557e973e5e28091c378e881. Tested-by: José Fonseca <[email protected]>
* llvmpipe: Simplify vertex and geometry shaders.José Fonseca2014-03-255-70/+33
| | | | | | | | | | | | Eliminate lp_vertex_shader, as it added nothing over draw_vertex_shader. Simplify lp_geometry_shader, as most of the incoming state is unneeded. (We could also just use draw_geometry_shader if we were willing to peek inside the structure.) Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Zack Rusin <[email protected]>
* radeonsi: disable fast color clear for 1D-tiled surfaces on CIKMarek Olšák2014-03-221-0/+6
| | | | This will be re-enabled once my kernel fix lands.
* llvmpipe: add support for b5g6r5_srgbRoland Scheidegger2014-03-212-4/+36
| | | | | | | | | | | | | The conversion code for srgb was tuned for n x 4x8bit AoS -> 4 x nxfloat SoA (and vice versa), fix this to handle also 16bit 565-style srgb formats. Still not really all that generic, things like r10g10b10a2_srgb or r4g4b4a4_srgb wouldn't work (the latter trivial to fix, the former would not require more work to not crash but near certainly need some higher precision calculation) but not needed right now. The code is not fully optimized for this (could use more direct calculation instead of expanding to 8-bit range first) but should be good enough. Reviewed-by: Jose Fonseca <[email protected]>
* nvc0/ir: move sample id to second source arg to fix sampler2DMSIlia Mirkin2014-03-202-4/+12
| | | | | | | | | | | | The nvc0 texfetch instruction expects the sample id to be in the second source (usually used for the offset) rather than as part of the texture coordinate. This fixes all the sampler2DMS/Array tests on nvc0. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Christoph Bumiller <[email protected]> Cc: "10.1" <[email protected]>
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