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* virgl: fix a sync issue in virgl_buffer_transfer_extendChia-I Wu2019-07-191-62/+15
* virgl: rework virgl_transfer_queue_extendChia-I Wu2019-07-193-25/+24
* virgl: fix virgl_buffer_transfer_extendChia-I Wu2019-07-191-0/+1
* radeonsi: initialize scissor registers etc. without clear stateMarek Olšák2019-07-191-1/+1
* radeonsi: return success from vi_dcc_clear_level to simplify callersMarek Olšák2019-07-193-28/+26
* radeonsi: fix compute-based culling regression in 1ce52c1e373Marek Olšák2019-07-191-1/+1
* radeonsi/gfx10: fix VGT_PRIMITIVE_TYPE programmingMarek Olšák2019-07-191-1/+3
* radeonsi/gfx10: enable Wave32 for vertex, geometry, and tessellation shadersMarek Olšák2019-07-191-0/+5
* radeonsi/gfx10: add debug options to enable/disable Wave32Marek Olšák2019-07-192-1/+35
* radeonsi/gfx10: add as_ngg variant for TES as ES to select Wave32/64Marek Olšák2019-07-194-15/+32
* radeonsi/gfx10: implement Wave32Marek Olšák2019-07-1915-71/+144
* radeonsi/gfx10: use 32-bit wavemasks for Wave32Marek Olšák2019-07-191-8/+20
* ac: create the LLVM builder in ac_llvm_context_initMarek Olšák2019-07-191-4/+3
* ac: create the LLVM module for Wave32 or Wave64 in ac_llvm_context_initMarek Olšák2019-07-191-2/+2
* ac/rtld: add support for Wave32Marek Olšák2019-07-193-0/+5
* ac: initial Wave32 support in LLVM build helpersMarek Olšák2019-07-191-1/+1
* radeonsi: assume that selector != NULL for compute shadersMarek Olšák2019-07-191-14/+6
* radeonsi: remove what appears to be legacy compute codeMarek Olšák2019-07-191-35/+6
* radeonsi: remove si_program::use_code_object_v2Marek Olšák2019-07-192-6/+3
* radeonsi: add si_shader_selector into si_computeMarek Olšák2019-07-194-81/+57
* radeonsi: set threadgroup size to 0 for threadgroups with only 1 waveMarek Olšák2019-07-191-3/+3
* radeonsi/gfx10: set as_ngg for GS prologMarek Olšák2019-07-192-5/+9
* radeonsi/gfx10: remove the disable_ngg optionMarek Olšák2019-07-193-6/+2
* radeonsi/gfx10: combine hw edgeflags with user edgeflags for correct behaviorMarek Olšák2019-07-194-19/+73
* radeonsi/gfx10: deduplicate code for esvert_lds_sizeMarek Olšák2019-07-191-6/+16
* radeonsi/gfx10: simplify a streamout loop in gfx10_emit_ngg_epilogueMarek Olšák2019-07-191-7/+6
* radeonsi/gfx10: don't use MALLOC for outputsMarek Olšák2019-07-191-9/+2
* radeonsi/gfx10: clean up ESGS ring size computationMarek Olšák2019-07-192-24/+11
* radeonsi/gfx10: fix unnecessary LDS overallocation for NGG GSMarek Olšák2019-07-192-8/+2
* radeonsi/gfx10: don't compile the GS copy shader if it's 100% not neededMarek Olšák2019-07-192-8/+12
* radeonsi/gfx10: set GE_CTNL.PACKET_TO_ONE_PA for NGGMarek Olšák2019-07-193-27/+27
* radeonsi/gfx10: update a tunable max_es_verts_base for NGGMarek Olšák2019-07-193-7/+12
* radeonsi/gfx10: implement ARB_post_depth_coverageMarek Olšák2019-07-192-1/+6
* radeonsi: fix leaked compute shader NIRMarek Olšák2019-07-191-0/+1
* radeonsi: save the enable_nir option in the shader cache correctlyMarek Olšák2019-07-191-5/+6
* radeonsi/gfx10: enable SDMAMarek Olšák2019-07-191-2/+0
* radeon/vcn: adding engine type for new fw interfaceBoyuan Zhang2019-07-193-2/+5
* radeonsi: use the correct buffer size in si_vid_clear_bufferMarek Olšák2019-07-191-1/+1
* util: use standard name for vsnprintf()Eric Engestrom2019-07-191-1/+1
* util: use standard name for snprintf()Eric Engestrom2019-07-1915-34/+34
* util: use standard name for sprintf()Eric Engestrom2019-07-193-3/+3
* lima/ppir: handle all node types in ppir_node_replace_childErico Nunes2019-07-191-2/+30
* lima/ppir: branch regalloc fixesErico Nunes2019-07-191-0/+33
* iris: change last_vue_stage() to look at uncompiled shadersTimothy Arceri2019-07-191-3/+3
* panfrost: Set rt_countAlyssa Rosenzweig2019-07-182-8/+11
* panfrost: Trace invisible BOsAlyssa Rosenzweig2019-07-181-1/+5
* panfrost: Zero polygon list body size for clearsAlyssa Rosenzweig2019-07-181-0/+4
* panfrost/mfbd: Unify depth-only with masked FBO pathAlyssa Rosenzweig2019-07-181-22/+24
* panfrost: Simplify set_framebuffer_stateAlyssa Rosenzweig2019-07-181-35/+9
* panfrost: Check for NULL surface in placesAlyssa Rosenzweig2019-07-185-5/+14
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