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* virgl: add memory barrier supportDave Airlie2018-08-015-0/+29
| | | | Reviwed-by: Gert Wollny <[email protected]>
* virgl: add TXQS supportDave Airlie2018-08-012-1/+3
| | | | Reviwed-by: Gert Wollny <[email protected]>
* virgl: add initial images support (v2)Dave Airlie2018-08-018-0/+105
| | | | | | v2: add max image samples support Reviwed-by: Gert Wollny <[email protected]>
* etnaviv: fix typo in query namesChristian Gmeiner2018-07-311-2/+2
| | | | | | | Fixes: d0bed0b4944d ("etnaviv: support HI performance counters") Cc: [email protected] Signed-off-by: Christian Gmeiner <[email protected]> Reviewed-by: Chris Healy <[email protected]>
* v3d: Include commands to run the BCL and RCL in CLIF dumps.Eric Anholt2018-07-301-10/+1
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* v3d: Rename "configuration" and "config" in the XML to "cfg"Eric Anholt2018-07-304-30/+33
| | | | | | This matches what CLIF parsing expects, and makes TILE_BINNING_MODE_CONFIGURATION_COMMON_CONFIGURATION into a much more legible TILE_BINNING_MODE_CFG_COMMON.
* v3d: s/colour/color in the XML.Eric Anholt2018-07-303-20/+20
| | | | | | The CLIF format expects american english spelling, and the rest of Mesa is too. I was previously adhering to the spec's spelling, which is counterproductive.
* v3d: Rename primitives to prims in the XML to match CLIF names.Eric Anholt2018-07-302-5/+5
| | | | This makes us match up with the V3D HW team's names a bit more.
* v3d: Add a separate flag for CLIF ABI output versus human-readable CLs.Eric Anholt2018-07-302-3/+4
| | | | | | A few of the upcoming changes would make the V3D_DEBUG=cl output less readable, so let's make proper CLIF file production be under a separate V3D_DEBUG=clif flag.
* v3d: Add pack header support for f187 values.Eric Anholt2018-07-302-15/+5
| | | | | | V3D only has one of these (the top 16 bits of a float32) left in its CLs, but VC4 had many more. This gets us proper pretty-printing of the values instead of a large uint.
* v3d: Move depth offset packet setup to CSO creation time.Eric Anholt2018-07-304-33/+34
| | | | | This should be some simpler memcpying at draw time, and makes the next change easier.
* r600: reduce num compute threads to 1024.Dave Airlie2018-07-311-1/+1
| | | | | | | | | | I copied this value from radeonsi, but it was wrong, 1024 seems to be correct answer from looking at gpuinfo. This should fix a few compute shader related hangs. (at least in CTS) Cc: <[email protected]> (airlied: pushed because it avoids hangs)
* freedreno/a5xx: fix txf_msRob Clark2018-07-303-0/+12
| | | | | | Somehow this got lost from the initial MSAA patch. Signed-off-by: Rob Clark <[email protected]>
* nvc0: serialize before updating some constant buffer bindings on Maxwell+Rhys Perry2018-07-304-47/+81
| | | | | | | | | | | | | | | | | To avoid serializing, this has the user constant buffer always be 65536 bytes and enabled unless it's required that something else is used for constant buffer 0. Fixes artifacts with at least XCOM: Enemy Within, 0 A.D. and Unigine Valley, Heaven and Superposition. v2: changed uniform_buffer_bound to be bool instead of a uint32_t v3: remove magic constants v3: remove pointless code in nvc0_validate_driverconst Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100177 Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* v3d: Block bin on render when doing vertex texturing.Eric Anholt2018-07-291-0/+14
| | | | | | | | | | | | The kernel by default serializes the BCL on previous BCLs submitted on this FD, but not RCLs. For now this fix is conservative and blocks on last RCL if any vertex texturing is done, which fails to get bin/render overlap if there was an intermediate job that doesn't draw to the BCL's buffer. I've dropped a perf_debug() in here to note that as a potential future improvement. Fixes intermittent failures in KHR-GLES3.copy_tex_image_conversions.required.*
* vc4: Fix meson build when enabled without v3d.Eric Anholt2018-07-291-1/+1
| | | | | Reported-by: Rob Clark <[email protected]> Fixes: e92959c4e03c ("v3d: Pass the whole clif_dump structure to v3d_print_group().")
* freedreno/a5xx: small cleanupRob Clark2018-07-291-26/+24
| | | | | | | | | | We no longer have semi-custom clear pipe that uses 3d state. Normal clears happen via hw blitter, and everything else uses u_blitter these days. So we don't need this hack. TODO a3xx+a4xx could get same treatment. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: remove unused prototypeRob Clark2018-07-291-3/+0
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: fix caps harderRob Clark2018-07-291-4/+4
| | | | | Fixes: 868ca81c and f485e567 Signed-off-by: Rob Clark <[email protected]>
* svga: whitespace fixes in svga_tgsi_decl_sm30.cBrian Paul2018-07-271-88/+92
| | | | Trivial.
* v3d: Stop doing pretty-printed colorful booleans in CLIF output.Eric Anholt2018-07-271-1/+1
| | | | | The parser wants to see a 1 or 0. We can put "true" and "false" in a comment to clarify that it's a boolean and the parser will skip it.
* v3d: Move clif dumping to a separate step from noting where the CLs are.Eric Anholt2018-07-271-0/+2
| | | | Now all the printing happens from the same worklist processing.
* v3d: Move clif dump BO lookup into the clif dumper.Eric Anholt2018-07-272-23/+16
| | | | | The clif dumper is going to need information about all of our BOs if we're going to dump them for replay purposes.
* v3d: Pass the whole clif_dump structure to v3d_print_group().Eric Anholt2018-07-271-1/+6
| | | | | | To generate CLIF files that the v3dv3 simulator can parse, we're going to need to decode addresses, and for that we'll need the vaddr lookup function from the clif structure from within v3d_decoder.
* v3d: Drop the use of the semaphores.Eric Anholt2018-07-272-9/+0
| | | | | | The kernel's scheduler doesn't rely on our emitting them, and in fact we'd get in trouble if the kernel decided to schedule too many bins in a row before getting around to scheduling the corresponding render.
* v3d: Drop the VG support from the XML.Eric Anholt2018-07-271-2/+1
| | | | | | This reflects a change on the HW/closed SW side to drop this unused HW. With it dropped on their side, the CLIF parser no longer expects to find VG fields.
* v3d: Stop using spaces in the names of our buffers.Eric Anholt2018-07-273-2/+6
| | | | | For CLIF dumping, we need names to not have spaces. Rather than rewriting them after the fact, just change the two cases where I had put a space in.
* v3d: Avoid the GFXH-1461 workaround if we have only Z or only S.Eric Anholt2018-07-261-4/+6
| | | | | | This seems like a sensible precaution to avoid extra draws. It doesn't deal with the case of a Z24S8 buffer created by the window system for an application that happens to never use S.
* v3d: Rework the ordering of how we clear things.Eric Anholt2018-07-261-31/+54
| | | | | | | | | First, figure out if we can just sneak the clear into the TLB clear, even if drawing has already happened (since we have job->load and job->clear to tell us), taking into account GFXH-1461. For any pieces we can't TLB clear, fall back to drawing a quad without flushing the scene. Fixes extra scene flushes in glmark2 due to GFXH-1461.
* v3d: Only store buffers that have been written to.Eric Anholt2018-07-261-3/+9
| | | | | I've seen cases where a color buffer is bound, but only Z is written, and we end up storing color.
* v3d: Track the buffers being loaded separately.Eric Anholt2018-07-263-1/+8
| | | | | | We were computing this at RCL generation time, but that means you can't unflag the store for an invalidate_resource, or not flag the store if writmasking is disabled.
* v3d: Rename cleared/resolve to clear/store.Eric Anholt2018-07-265-35/+35
| | | | | | These describe what the fields mean in RCL generation. "resolve" is left over from VC4, and sounds like MSAA resolves (which may or may not be involved in the store we generate).
* ac: fix typo DSL_SEL -> DST_SELMarek Olšák2018-07-261-2/+2
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* radeonsi: update a comment about cache behaviorMarek Olšák2018-07-261-3/+3
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* r600: Scale integer valued texture border colors to float (v2)Gert Wollny2018-07-251-1/+44
| | | | | | | | | | | | | | | | | | | | | | | | It seems the hardware always expects floating point border color values [0,1] for unsigned, and [-1,1] for signed texture component, regardless of pixel type, but the border colors are passed according to texture component type. Hence, before submitting the border color, convert and scale it these ranges accordingly. This doesn't seem to work for textures with 32 bit integer components though, here, it seems that the border color is always set to zero, regardless of the BORDER_COLOR_TYPE state set in Q_TEX_SAMPLER_WORD0_0. v2: Simplyfy logic as suggested by Roland Schneidegger Fixes: dEQP-GLES31.functional.texture.border_clamp.formats.compressed* dEQP-GLES31.functional.texture.border_clamp.formats.r* (non 32 bit integer) dEQP-GLES31.functional.texture.border_clamp.per_axis_wrap_mode.texture_2d* and a number of piglits out of piglit run gpu -t texture -t gather -t formats Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* nir: rename f2f16_undef to f2f16Karol Herbst2018-07-241-3/+3
| | | | | | | | | | | we need rounding modes on other conversions involving floats and it is easier to rename f2f16_undef than renaming all the other ones. v2: rebased on master Reviewed-by: Jason Ekstrand <[email protected]> Acked-by: Rob Clark <[email protected]> Signed-off-by: Karol Herbst <[email protected]>
* radeonsi: handle SI_FORCE_FAMILY earlyMarek Olšák2018-07-241-2/+1
| | | | before LLVM target machines are created
* forward precise-flag if supportedErik Faye-Lund2018-07-242-1/+5
| | | | | | | | | | | | | | | | New versions of virglrenderer supports the precise-flag, so let's forward it from TGSI if that's the case. This fixes a few dEQP-GLES31 tests: - dEQP-GLES31.functional.tessellation.common_edge.quads_equal_spacing_precise - dEQP-GLES31.functional.tessellation.common_edge.quads_fractional_even_spacing_precise - dEQP-GLES31.functional.tessellation.common_edge.quads_fractional_odd_spacing_precise - dEQP-GLES31.functional.tessellation.common_edge.triangles_equal_spacing_precise - dEQP-GLES31.functional.tessellation.common_edge.triangles_fractional_even_spacing_precise - dEQP-GLES31.functional.tessellation.common_edge.triangles_fractional_odd_spacing_precise Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radeonsi: fix pk2h breakageMarek Olšák2018-07-231-2/+5
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* radeonsi: reduce LDS stalls by 40% for tessellationMarek Olšák2018-07-234-6/+14
| | | | | | | | 40% is the decrease in the LGKM counter (which includes SMEM too) for the GFX9 LSHS stage. This will make the LDS size slightly larger, but I wasn't able to increase the patch stride without corruption, so I'm increasing the vertex stride.
* radeonsi: Add debug option to enable LLVM GlobalISel (v2)Tom Stellard2018-07-232-0/+4
| | | | | | | | | | R600_DEBUG=gisel will tell LLVM to use GlobalISel rather than SelectionDAG for instruction selection. v2: mareko: move the helper to src/amd/common Signed-off-by: Marek Olšák <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* r600: enable tess_input_info for TESDave Airlie2018-07-231-14/+6
| | | | | | | | | | | There might be a nicer way to do this, but this is at least correct. This fixes: KHR-GL44.tessellation_shader.single.max_patch_vertices KHR-GL44.tessellation_shader.tessellation_control_to_tessellation_evaluation.gl_PatchVerticesIn Reviewed-By: Gert Wollny <[email protected]> Cc: [email protected]
* Revert "virgl: remove unused stride-arguments"Dave Airlie2018-07-244-5/+27
| | | | | | This reverts commit dc938b8398c0dafb60507e41685f7518b681c24d. This adds warnings in vtest, and possibly breaks it.
* virgl: add initial shader_storage_buffer_object support. (v2)Dave Airlie2018-07-249-0/+98
| | | | | | | | | | | This adds the guest side support for ARB_shader_storage_buffer_object. Co-authors: Gurchetan Singh <[email protected]> v2: move to using separate maximums (fixup macros) Reviewed-By: Gert Wollny <[email protected]>
* virgl: remove unused stride-argumentsErik Faye-Lund2018-07-234-27/+5
| | | | | | | | The IOCTLs doesn't pass this along, so computing them in the first place is kinda pointless. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* radeonsi/nir: make use of nir_lower_load_const_to_scalar()Timothy Arceri2018-07-231-0/+2
| | | | | | | | | This allows NIR to CSE more operations. LLVM does this also so the impact is limited, however doing this in NIR allows other opts to make progress. For example some loops in Civilization Beyond Earth shaders are unrolled. Reviewed-by: Marek Olšák <[email protected]>
* Android: fix a missing nir_intrinsics.h errorChih-Wei Huang2018-07-211-0/+2
| | | | | | | | | | | | | | | | | | | | | The commit 76dfed8ae2d5 changed nir_intrinsics.h to be a generated header, but the corresponding dependency was not updated for Android. It causes the error: [ 0% 19/4336] target C: libmesa_pipe_radeonsi <= external/mesa/src/gallium/drivers/radeonsi/si_debug.c ... In file included from external/mesa/src/gallium/drivers/radeonsi/si_debug.c:25: In file included from external/mesa/src/gallium/drivers/radeonsi/si_pipe.h:28: In file included from external/mesa/src/gallium/drivers/radeonsi/si_shader.h:140: In file included from external/mesa/src/amd/common/ac_llvm_build.h:30: external/mesa/src/compiler/nir/nir.h:966:10: fatal error: 'nir_intrinsics.h' file not found ^~~~~~~~~~~~~~~~~~ 1 error generated. Fixes: 76dfed8ae2d5 ("nir: mako all the intrinsics") Signed-off-by: Chih-Wei Huang <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Mauro Rossi <[email protected]>
* v3d: Fix incorrect handling of two fences created back-to-back.Eric Anholt2018-07-201-12/+31
| | | | | | | | | | | Recreating our context's syncobj with ALREADY_SIGNALED meant that if you created two fences in a row, then waiting on the second would succeed immediately. Instead, export a sync file in the gallium fence (since we don't have a syncobj clone ioctl), and just create a new syncobj to wait on whenever we need to. Noticed while debugging dEQP-GLES3.functional.fence_sync.client_wait_sync_finish
* v3d: Fix the timeout value passed to drmSyncobjWait().Eric Anholt2018-07-201-1/+6
| | | | | The API wants an absolute time, so we need to go add gallium's argument to CLOCK_MONOTONIC.
* v3d: Fix drmSyncobjWait() return value checking even more.Eric Anholt2018-07-201-1/+1
| | | | | | It tends to return >0 in the success case (I think the value is something like "how much of the timeout remained"). Fixes dEQP-GLES3.functional.fence_sync.client_wait_sync_finish
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