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* radeonsi: fix an out-of-bounds read reported by ASANNicolai Hähnle2018-11-191-0/+4
* r600: Only set context streamout strides info from the shader that has outputsGert Wollny2018-11-191-3/+9
* virgl: Clean up fences commitRobert Foss2018-11-181-1/+1
* nv50/ir/ra: enforce max register requirement, and change spill orderIlia Mirkin2018-11-164-16/+26
* nv50/ir/ra: improve condition for short regs, unify with cond for 16-bitIlia Mirkin2018-11-161-7/+7
* nv50/ir: delete MINMAX instruction that is no longer in the BBIlia Mirkin2018-11-161-1/+1
* virgl: native fence fd supportRobert Foss2018-11-163-10/+62
* vc4: Don't return a vc4 BO handle on a renderonly screen.Eric Anholt2018-11-151-2/+4
* vc4: Make sure we make ro scanout resources for create_with_modifiers.Eric Anholt2018-11-151-1/+9
* v3d: Fix double-swapping of R/B on V3D 4.1Eric Anholt2018-11-151-2/+3
* etnaviv: Make sure rs alignment checks matchGuido Günther2018-11-151-6/+13
* radeonsi: fix video APIs on Raven2Marek Olšák2018-11-142-4/+8
* virgl: Add command and flags to initiate debugging on the host (v2)Gert Wollny2018-11-135-0/+37
* freedreno/drm: fix unused 'entry' warningsRob Clark2018-11-121-2/+0
* radeonsi: stop command submission with PIPE_CONTEXT_LOSE_CONTEXT_ON_RESET onlyMarek Olšák2018-11-0912-17/+20
* radeonsi: don't set the CB clear color registers for 0/1 clear colors on Raven2Marek Olšák2018-11-094-3/+11
* radeonsi: use better DCC clear codesMarek Olšák2018-11-091-5/+21
* gm107/ir: fix compile time warning in getTEXSMaskKarol Herbst2018-11-071-0/+1
* gm107/ir: use scalar tex instructions where possibleKarol Herbst2018-11-062-3/+317
* nv50/ir: add scalar field to TexInstructionsKarol Herbst2018-11-062-1/+6
* nv50/ra: add condenseDef overloads for partial condensesKarol Herbst2018-11-061-8/+21
* nv50/ir: print color masks of tex instructionsKarol Herbst2018-11-061-4/+33
* r600: Add support for EXT_texture_sRGB_R8Gert Wollny2018-11-061-0/+1
* freedreno/a6xx: Clear z32 and separate stencil with blitterKristian H. Kristensen2018-11-062-27/+50
* freedreno/a6xx: fix VSC bug with larger # of tilesRob Clark2018-11-061-5/+2
* freedreno: update generated headersRob Clark2018-11-067-29/+51
* r600/sb: Fix constant logical operand in assert.Vinson Lee2018-11-041-1/+1
* vc4: Use the normal simulator ioctl path for CL submit as well.Eric Anholt2018-11-023-13/+5
* vc4: Maintain a separate GEM mapping of BOs in the simulator.Eric Anholt2018-11-022-42/+58
* vc4: Take advantage of _mesa_hash_table_remove_key() in the simulator.Eric Anholt2018-11-021-4/+2
* v3d: Remove the special path for simulaton of the submit ioctl.Eric Anholt2018-11-025-19/+13
* v3d: Maintain a mapping of the GEM buffer in the simulator.Eric Anholt2018-11-021-23/+48
* Gallium: Add format PIPE_FORMAT_R8_SRGBGert Wollny2018-11-021-0/+1
* vc4: Drop the winsys_stride relayout in the simluatorEric Anholt2018-11-015-95/+12
* v3d: Use the TLB R/B swapping instead of recompiles when available.Eric Anholt2018-11-014-3/+17
* v3d: Take advantage of _mesa_hash_table_remove_key() in the simulator.Eric Anholt2018-11-011-4/+2
* v3d: Respect user-passed strides for BO imports.Eric Anholt2018-11-015-96/+19
* v3d: Drop #if 0-ed out v3d_dump_to_file().Eric Anholt2018-11-011-91/+0
* v3d: Fix a typo in a comment in job handling.Eric Anholt2018-11-011-1/+1
* v3d: Fix a copy-and-paste comment in the simulator code.Eric Anholt2018-11-011-1/+1
* freedreno: Do not link ir3_compiler with valgrind libraries.Vinson Lee2018-10-311-2/+1
* configure: allow building with python3Emil Velikov2018-10-314-4/+4
* util: Move os_misc to utilDylan Baker2018-10-305-5/+5
* radeonsi: add support for Raven2 (v2)Marek Olšák2018-10-303-5/+10
* radeonsi: clean up decompress flags in fast color clearMarek Olšák2018-10-301-11/+7
* radeonsi/gfx9: set optimal OVERWRITE_COMBINER_WATERMARKMarek Olšák2018-10-302-1/+14
* gallium: rework PIPE_HANDLE_USAGE_* flagsMarek Olšák2018-10-304-7/+7
* nouveau: remove unused class memberEric Engestrom2018-10-301-1/+0
* scons: drop unused HAVE_STDINT_H macroEric Engestrom2018-10-302-10/+0
* vc4: Fix unused variable warning.Eric Anholt2018-10-301-1/+0
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