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* radeonsi: remove nr_vertex_buffersMarek Olšák2014-07-183-6/+23
| | | | | | | | Unused. Also inline util_set_vertex_buffers_count and simplify it. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: move vertex buffer descriptors from IB to memoryMarek Olšák2014-07-187-106/+133
| | | | | | | | | | This removes the intermediate storage (pm4 state) and generates descriptors directly in a staging buffer. It also reduces the number of flushes, because the descriptors no longer take CS space. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: add support for fine-grained sampler view updatesMarek Olšák2014-07-183-30/+21
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: move si_set_sampler_views to si_descriptors.cMarek Olšák2014-07-183-73/+68
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: move sampler descriptors from IB to memoryMarek Olšák2014-07-185-82/+82
| | | | | | | | | | | | | | Sampler descriptors are now represented by si_descriptors. This also adds support for fine-grained sampler state updates and the border color update is now isolated in a separate function. Border colors have been broken if texturing from multiple shader stages is used. This patch doesn't change that. BTW, blitting already makes use of fine-grained state updates. u_blitter uses 2 textures at most, so we only have to save 2. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: implement ARB_draw_indirectMarek Olšák2014-07-185-17/+128
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: don't add info->start to the index buffer offsetMarek Olšák2014-07-181-11/+25
| | | | | | | info->start will be invalid once info->indirect isn't NULL, so it shouldn't be added to ib.offset. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: use an SGPR instead of VGT_INDX_OFFSETMarek Olšák2014-07-184-14/+23
| | | | | | | | The draw indirect packets cannot set VGT_INDX_OFFSET, they can only set user data SGPRs. This is the only way to support start/index_bias with indirect drawing. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: assume LLVM 3.4.2 is always presentMarek Olšák2014-07-186-56/+7
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* r600g: Implement GL_ARB_texture_gatherGlenn Kennard2014-07-182-7/+42
| | | | | | | | | | | | Only supported on evergreen and later. Currently limited to single component textures as the hardware GATHER4 instruction ignores texture swizzles. Piglit quick run passes on radeon 6670 with all applicable textureGather tests, no regressions. Signed-off-by: Glenn Kennard <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* nv50: fix build failure on m68k due to invalid struct alignment assumptionsThorsten Glaser2014-07-171-0/+5
| | | | | | | | Make alignment assumptions explicit by inserting correct padding with unknown struct members. Reviewed-by: Ilia Mirkin <[email protected]> Cc: <[email protected]>
* ilo: add some missing formatsChia-I Wu2014-07-161-21/+22
| | | | Map more pipe formats to hardware formats. Enable more VB formats on Haswell.
* ilo: update and tailor the surface format tableChia-I Wu2014-07-161-286/+258
| | | | | Recreate the table from scratch with the help of a pdf-table-to-csv converter. Switch to a form that is more suitable for ilo.
* nvc0: fix translate path for PRIM_RESTART_WITH_DRAW_ARRAYSChristoph Bumiller2014-07-151-13/+28
| | | | Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: add support for indirect drawingChristoph Bumiller2014-07-158-30/+220
| | | | Reviewed-by: Ilia Mirkin <[email protected]>
* nouveau: check if a fence has already been signalledIlia Mirkin2014-07-151-0/+3
| | | | | | | nouveau_fence_update does real work unconditionally. Avoid doing that if the fence we're checking on has already been signalled. Signed-off-by: Ilia Mirkin <[email protected]>
* radeon/llvm: Fix LLVM diagnostic error reportingTom Stellard2014-07-151-7/+4
| | | | | | | We were trying to print the error message after disposing the message object. Tested-by and Reviewed-by: Aaron Watry <[email protected]>
* ilo: raise texture size limitsChia-I Wu2014-07-152-17/+9
| | | | | Report the hardware limits now that max-texture-size piglit test has been fixed.
* ilo: move away from drm_intel_bo_alloc_tiledChia-I Wu2014-07-153-250/+300
| | | | | We want to know the exact sizes of the BOs, and the driver has the knowledge to do so. Refactoring of the resource allocation code is needed though.
* radeonsi: partially revert "switch descriptors to i32 vectors"Marek Olšák2014-07-141-0/+12
| | | | It indeed breaks LLVM 3.4.2.
* radeonsi: rename definitions of shader limitsMarek Olšák2014-07-117-44/+57
| | | | Reviewed-by: Tom Stellard <[email protected]>
* radeonsi: switch descriptors to i32 vectorsMarek Olšák2014-07-111-13/+16
| | | | | | This is a follow-up to the commit which adds texture fetches with offsets. Reviewed-by: Tom Stellard <[email protected]>
* radeonsi: properly implement texture opcodes that take an offsetMarek Olšák2014-07-111-84/+104
| | | | | | | | | | | | Instead of using intr_name in lp_build_tgsi_action, this selects the names with a switch statement in the emit function. This allows emitting llvm.SI.sample for instructions without offsets and llvm.SI.image.sample.*.o otherwise. This depends on my LLVM changes. When LLVM 3.5 is released, I'll switch all texture instructions to the new intrinsics.
* radeonsi: fix texture fetches with derivatives for 1DArray and 3D texturesMarek Olšák2014-07-111-4/+30
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* radeonsi: fix samplerCubeShadow with biasMarek Olšák2014-07-111-6/+6
| | | | | | Pack the depth value before overwriting it with cube coordinates. Cc: [email protected]
* softpipe: fix sp_get_dims() for PIPE_BUFFERBrian Paul2014-07-101-6/+10
| | | | | | | | | | | | Before, we were checking the level against view->u.tex.last_level but level is not valid for buffers. Plus, the aliasing of the view->u.tex view->u.buf members (a union) caused the level checking arithmetic to be totally wrong. The net effect is we always returned early for PIPE_BUFFER size queries. This fixes the piglit "textureSize 140 fs samplerBuffer" test. Reviewed-by: Roland Scheidegger <[email protected]>
* nvc0/ir: add support for interpolating with non-default settingsIlia Mirkin2014-07-093-1/+94
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* r600g: remove unused base_vector_chan variableIlia Mirkin2014-07-091-1/+0
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* nvc0/ir: fix encoding of offset register into interpolation instructionIlia Mirkin2014-07-091-1/+1
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: account for indirect textures on fermi for txdIlia Mirkin2014-07-091-0/+3
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: unset s/r indirect sources before moving everythingIlia Mirkin2014-07-091-9/+10
| | | | | | | | | With the current logic, it's very likely that s/r indirect sources are right after the "regular" ones. Unset them before moving the texture arguments over rather than after, as one of those arguments would likely have assumed one of the s/r positions. Signed-off-by: Ilia Mirkin <[email protected]>
* gallium: switch dedicated centroid field to interpolation locationIlia Mirkin2014-07-094-7/+7
| | | | | | | | The new location field can be either center, centroid, or sample, which indicates the location that the shader should interpolate at. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* radeonsi: fix order of r600_need_dma_space and r600_context_bo_relocChristian König2014-07-091-1/+2
| | | | | Signed-off-by: Christian König <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* nvc0: allocate more space before a counter is configuredSamuel Pitoiset2014-07-081-2/+3
| | | | | | | | | On nvc0, a counter can have up to 6 sources instead of only one for nve4+. This fixes a crash when a counter uses more than one source. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50/ir: use unordered_set instead of list to keep track of var usesTobias Klausmann2014-07-084-9/+10
| | | | | | | | | | | The set of variable uses does not need to be ordered in any way, and removing/adding elements is a fairly common operation in various optimization passes. This shortens runtime of piglit test fp-long-alu to ~22s from ~4h Signed-off-by: Tobias Klausmann <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* radeonsi: mark MSAA config state as dirty at the beginning of CSMarek Olšák2014-07-081-0/+1
| | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=81020 Reviewed-by: Alex Deucher <[email protected]>
* ilo: fix fence reference countingChia-I Wu2014-07-081-12/+9
| | | | The old code was complicated, and was wrong when *ptr is NULL.
* nvc0/ir: fill offset in properly for TXDIlia Mirkin2014-07-081-13/+43
| | | | | | | | Apparently TXD wants its offset differently than TEX, accepting it in the upper bits of the layer index. Unclear what happens when this is combined with indirect sampler indexing. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: use manual TXD when offsets are involvedIlia Mirkin2014-07-081-1/+2
| | | | | | | | | | Something about how we're implementing offsets for TXD is wrong, just flip to the generic quadop-based implementation in that case. This is the minimal fix appropriate for backporting. Signed-off-by: Ilia Mirkin <[email protected]> Cc: <[email protected]>
* nvc0/ir: do quadops on the right texture coordinates for TXDIlia Mirkin2014-07-081-2/+3
| | | | | | | | handleTEX moves the layer as the first argument. This makes sure that the quadops deal with the texture coordinates. Signed-off-by: Ilia Mirkin <[email protected]> Cc: <[email protected]>
* nv50/ir: ignore bias for samplerCubeShadow on nv50Ilia Mirkin2014-07-081-0/+10
| | | | | | | | Unfortunately there's no good way to do this on the nv50 shader isa. Dropping the bias seems preferable to doing the compare post-filtering. Signed-off-by: Ilia Mirkin <[email protected]> Cc: <[email protected]>
* nv50/ir: retrieve shadow compare from first argIlia Mirkin2014-07-081-1/+1
| | | | | | | | This can only happen with texture(samplerCubeShadow, bias), where the compare will be in the first argument. Signed-off-by: Ilia Mirkin <[email protected]> Cc: <[email protected]>
* gallium/radeon: use PRIX64 instead of PRIu64Christian König2014-07-062-2/+2
| | | | | | | We want hex values here, not decimals. Signed-off-by: Christian König <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* nvc0: add a memory barrier when there are persistent UBOsIlia Mirkin2014-07-035-4/+57
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.2" <[email protected]>
* nv50: do an explicit flush on draw when there are persistent buffersIlia Mirkin2014-07-033-2/+50
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.2" <[email protected]>
* nv50: disable dedicated ubo upload methodIlia Mirkin2014-07-031-0/+7
| | | | | | | | | | The hardware allows multiple simultaneous renders with the same memory-backed constbufs but with each invocation having different values. However in order for that to work, the data has to be streamed in via the right constbuf slot. We weren't doing that for UBOs. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.2 10.1" <[email protected]>
* gallium: rename PIPE_CAP_TGSI_VS_LAYER to also have _VIEWPORTIlia Mirkin2014-07-0312-12/+12
| | | | | | | | | Now that this cap is used to determine the availability of both, adjust its name to reflect the new reality. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* r600g: allow vs to write to gl_ViewportIndexIlia Mirkin2014-07-031-0/+17
| | | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Tested-by: Tobias Droste <[email protected]>
* svga: Don't unnecessarily reemit BindGBShader commands v2Thomas Hellstrom2014-07-033-20/+8
| | | | | | | | | | | | | The Linux winsys can no longer relocate shader code, so avoid reemitting BindGBShader commands. They are costly. v2: Correctly handle errors from SVGA3D_BindGBShader() Reported-by: Michael Banack <[email protected]> Signed-off-by: Thomas Hellstrom <[email protected]> Tested-by: Brian Paul <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Jakob Bornecrantz <[email protected]>
* radeon/llvm: Allocate space for kernel metadata operandsAaron Watry2014-07-031-3/+7
| | | | | | | | | | | | | | | | | | Previously, we were assuming that kernel metadata nodes only had 1 operand. Kernels which have attributes can have more than 1, e.g.: !0 = metadata !{void (i32 addrspace(1)*)* @testKernel, metadata !1} !1 = metadata !{metadata !"work_group_size_hint", i32 4, i32 1, i32 1} Attempting to get the kernel without the correct number of attributes led to memory corruption and luxrays crashing out. Fixes the cl/program/execute/attributes.cl piglit test. Signed-off-by: Aaron Watry <[email protected]> Reviewed-by: Tom Stellard <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76223 CC: "10.2" <[email protected]>
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