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* radeonsi: make sure CP DMA is idle at the end of IBsMarek Olšák2018-04-133-2/+16
* radeonsi: always prefetch later shaders after the draw packetMarek Olšák2018-04-133-26/+75
* radeonsi: emit shader pointers before cache flushes & waitsMarek Olšák2018-04-131-13/+7
* radeonsi/gfx9: don't use the workaround for gather4 + stencilMarek Olšák2018-04-131-2/+11
* radeonsi: disable TC-compat HTILE on Tonga and IcelandMarek Olšák2018-04-131-0/+7
* radeonsi: force 2D tiling on VI only when TC-compat HTILE is really enabledMarek Olšák2018-04-131-9/+7
* radeonsi: don't flush HTILE if there is no HTILE clearMarek Olšák2018-04-131-2/+2
* radeonsi: merge 2 identical if statements in si_clearMarek Olšák2018-04-131-9/+2
* radeonsi: don't do GFX-specific texture decompression for computeMarek Olšák2018-04-131-10/+10
* radeonsi: simplify generating the renderer stringMarek Olšák2018-04-131-11/+8
* broadcom/vc5: Fix a stray '`' in a comment.Eric Anholt2018-04-121-1/+1
* broadcom/vc5: Update the UABI for in/out syncobjsEric Anholt2018-04-129-90/+55
* broadcom/vc5: Drop the finished_seqno optimization.Eric Anholt2018-04-122-11/+0
* broadcom/vc5: Drop the throttling code.Eric Anholt2018-04-121-9/+0
* broadcom/vc5: Move flush_last_load into load_general, like for stores.Eric Anholt2018-04-121-28/+29
* broadcom/vc5: Rename read_but_not_cleared to loads_pending.Eric Anholt2018-04-121-13/+13
* broadcom/vc5: Refactor the implicit coords/stores_pending logic.Eric Anholt2018-04-121-23/+13
* broadcom/vc5: Emit missing TILE_COORDINATES_IMPLICIT in separate z/s stores.Eric Anholt2018-04-121-5/+16
* broadcom/vc5: Add checks that we don't try to do raw Z+S load/stores.Eric Anholt2018-04-121-0/+8
* broadcom/vc5: Fix MSAA depth/stencil size setup.Eric Anholt2018-04-121-2/+4
* radeonsi: use PIPE_FORMAT_P016 format for VP9 profile2Leo Liu2018-04-121-1/+2
* radeon/vcn: add VP9 profile2 supportLeo Liu2018-04-121-0/+16
* radeonsi: cap VP9 support to progressive bufferLeo Liu2018-04-121-0/+2
* radeonsi: cap VP9 support to RavenLeo Liu2018-04-121-0/+4
* radeon/vcn: add VP9 context bufferLeo Liu2018-04-121-0/+26
* radeon/vcn: get VP9 msg bufferLeo Liu2018-04-122-1/+176
* radeon/vcn: fill probability table to prob buffersLeo Liu2018-04-121-0/+38
* radeon/vcn: add VP9 message buffer interfaceLeo Liu2018-04-121-0/+134
* radeon/vcn: add VP9 prob table bufferLeo Liu2018-04-122-18/+37
* radeon/vcn: add VP9 dpb buffer sizeLeo Liu2018-04-121-0/+6
* radeon/vcn: add VP9 stream type for decoderLeo Liu2018-04-122-0/+4
* radeonsi: correctly parse disassembly with labelsNicolai Hähnle2018-04-111-31/+32
* radeonsi: pass -O halt_waves to umr for hang debuggingNicolai Hähnle2018-04-111-2/+2
* radeonsi: add shader binary padding for UMRMarek Olšák2018-04-101-3/+15
* radeonsi: autotools: add si_build_pm4.h in dist tarballJuan A. Suarez Romero2018-04-101-0/+1
* radeonsi/nir: tidy up si_nir_load_sampler_desc()Timothy Arceri2018-04-101-5/+3
* radeonsi/nir: set uses_bindless_images for imagesTimothy Arceri2018-04-101-1/+16
* radeonsi/nir: don't add bindless samplers/images to declared bitmasksTimothy Arceri2018-04-101-6/+6
* radeonsi: convert dispatch packet to little endianBas Vermeulen2018-04-091-12/+12
* radeonsi: correct si_vgt_param_key on big endian machinesBas Vermeulen2018-04-091-0/+13
* radeonsi: don't set RB+ registers on GFX9 chips without RB+Marek Olšák2018-04-091-6/+1
* etnaviv: meson: add etnaviv_query_pm.[ch] to the sourcesEmil Velikov2018-04-091-0/+2
* etnaviv: expose perfmon query groupsChristian Gmeiner2018-04-081-2/+6
* etnaviv: add query_group_info for perfmon countersChristian Gmeiner2018-04-082-0/+50
* etnaviv: assign group_ids to perfmon queriesChristian Gmeiner2018-04-082-1/+56
* etnaviv: support MC performance countersChristian Gmeiner2018-04-082-0/+25
* etnaviv: support TX performance countersChristian Gmeiner2018-04-082-0/+73
* etnaviv: support RA performance countersChristian Gmeiner2018-04-082-0/+57
* etnaviv: support SE performance countersChristian Gmeiner2018-04-082-0/+17
* etnaviv: support PA performance countersChristian Gmeiner2018-04-082-0/+49
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