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* nvc0: disable MS Images for sample_count == 1 on MaxwellKarol Herbst2018-02-151-1/+1
* radeonsi/nir: fix si_nir_load_tcs_varyings() for outputsTimothy Arceri2018-02-151-2/+11
* radeonsi/nir: fix shader ballot return value bitsizeTimothy Arceri2018-02-151-1/+1
* ac: remove nir_to_llvm_context from ac_nir_translate()Samuel Pitoiset2018-02-141-1/+1
* r600: fix regression in gl_FragColor drawingDave Airlie2018-02-141-0/+2
* r600: fix array spill if temp[0] is before all arraysDave Airlie2018-02-141-0/+2
* virgl: add ARB_sample_shading support.Dave Airlie2018-02-143-3/+6
* virgl: add ARB_draw_indirect support.Dave Airlie2018-02-143-2/+28
* gallium: drop all the guard band float caps.Dave Airlie2018-02-1414-72/+0
* virgl: Support v2 caps struct (v2)Stéphane Marchesin2018-02-132-12/+45
* radeonsi: make si_declare_compute_memory() more generic and call for nirTimothy Arceri2018-02-134-7/+18
* ac: remove unused parameters in abi::load_tess_coord()Samuel Pitoiset2018-02-121-4/+2
* ac: add load_sample_mask_in() to the ABISamuel Pitoiset2018-02-121-0/+6
* freedreno: small fix for flushing dependent batchesRob Clark2018-02-101-0/+13
* freedreno/ir3: intra-block schedulingRob Clark2018-02-101-22/+104
* freedreno/ir3: "boost" the depth of if/else conditionRob Clark2018-02-101-5/+6
* freedreno/ir3: account for arrays in delayslot calcRob Clark2018-02-101-2/+30
* freedreno/ir3: more clever legalize algorithmRob Clark2018-02-101-42/+96
* freedreno/ir3: track block predecessorsRob Clark2018-02-102-7/+25
* freedreno/ir3: clean up dangling false-dep'sRob Clark2018-02-102-0/+46
* freedreno/ir3: handle IMMED for mad 2nd src special caseRob Clark2018-02-101-2/+4
* freedreno/ir3: remove ir3 phi instructionRob Clark2018-02-108-205/+16
* freedreno/ir3: remove lower_if_else passRob Clark2018-02-104-328/+0
* freedreno/ir3: add experimental GCM passRob Clark2018-02-101-0/+7
* freedreno/ir3: change opt passesRob Clark2018-02-101-0/+14
* freedreno/ir3: use peephole select passRob Clark2018-02-101-1/+1
* freedreno/ir3: lower phi webs to regsRob Clark2018-02-101-2/+1
* freedreno/ir3: separate arrays from groupsRob Clark2018-02-101-0/+8
* freedreno/ir3: make block/instruction serialno per-shaderRob Clark2018-02-102-4/+6
* freedreno/ir3: add spirv support to cmdline compilerRob Clark2018-02-101-3/+60
* freedreno/ir3: don't lower fsatRob Clark2018-02-103-1/+23
* freedreno/ir3: add encoding/decoding for (sat) bitRob Clark2018-02-104-12/+42
* freedreno/ir3: extend liverange of arraysRob Clark2018-02-101-0/+11
* freedreno/ir3: avoid extra mov's for "arrays"Rob Clark2018-02-101-3/+23
* freedreno/ir3: a couple more array fixesRob Clark2018-02-101-2/+15
* freedreno/ir3: keep array storesRob Clark2018-02-101-0/+6
* freedreno/ir3: propagate barrier informationRob Clark2018-02-101-0/+5
* freedreno/ir3: remove pointless statementRob Clark2018-02-101-3/+0
* freedreno/ir3: some more debug printsRob Clark2018-02-102-0/+36
* freedreno/ir3: fix printing of relative branch offsetsRob Clark2018-02-102-3/+3
* freedreno/ir3: be more clever with if/else jumpsRob Clark2018-02-101-1/+16
* freedreno/ir3: avoid some spurious sync bitsRob Clark2018-02-101-1/+3
* freedreno/ir3: print # of sync bits for shaderdbRob Clark2018-02-103-2/+18
* freedreno: add debug trace for flushRob Clark2018-02-101-0/+2
* st/radeonsi: enable disk cache for nirTimothy Arceri2018-02-101-4/+0
* radeonsi: stop returning PIPE_SHADER_IR_NATIVE for PIPE_SHADER_CAP_PREFERRED_IRTimothy Arceri2018-02-101-3/+0
* r600: always return PIPE_SHADER_IR_TGSI for PIPE_SHADER_CAP_PREFERRED_IRTimothy Arceri2018-02-101-5/+1
* r600: add PIPE_SHADER_IR_NATIVE to supported shaders for csTimothy Arceri2018-02-101-3/+7
* radeonsi/nir: add depth layout to scan passTimothy Arceri2018-02-101-0/+19
* radeonsi/nir: add FRAG_RESULT_COLOR to scan passTimothy Arceri2018-02-101-0/+6
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