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* ilo: add a new struct for context statesChia-I Wu2014-09-2020-654/+672
| | | | | | | | | | Move pipe states in ilo_context to the new ilo_state_vector. The motivation is that ilo_context consists of several loosely related things. When we need an ilo_context somewhere, we usually need only one or two of the things in it. This change makes ilo_state_vector one such thing. An immediate result is that we no longer need ilo_context in 3D pipelines, something we have planned for since early days.
* ilo: merge ilo_gpe.h to ilo_state*.hChia-I Wu2014-09-2013-544/+513
| | | | | Move the #define's and struct's to ilo_state.h. Move the inline functions and function declarations to ilo_state_gen.h.
* ilo: rename ilo_gpe_gen*.[ch]Chia-I Wu2014-09-205-9/+9
| | | | Rename them to ilo_state_gen*.[ch].
* ilo: make ilo_fence opaqueChia-I Wu2014-09-202-5/+7
| | | | It is manipulated only in ilo_screen.c.
* vc4: Fix perspective interpolation.Eric Anholt2014-09-191-1/+1
| | | | Fixes the mesa reflect demo and 6 tests under interpolation/
* vc4: Use the same method as for FRAG_Z to handle fragcoord W.Eric Anholt2014-09-195-13/+15
| | | | I need to get the non-reciprocal version of W for interpolation, anyway.
* ilo: rename ILO_DEBUG=3dChia-I Wu2014-09-195-6/+6
| | | | | | It has been a bad name since we added the builder. Rename it to ILO_DEBUG=batch to match i965, and call ilo_builder_decode() from ilo_cp_submit_internal().
* ilo: rename ilo_cp_flush()Chia-I Wu2014-09-1911-52/+52
| | | | | | "Flush" is used for too many things already: pipe resource flush, pipe context flush, pipe transfer region flush, and hardware pipeline flush. Rename it to ilo_cp_submit(). As such, ILO_DEBUG=flush is renamed to ILO_DEBUG=submit.
* ilo: remove ilo_cp_empty()Chia-I Wu2014-09-193-22/+12
| | | | Call ilo_builder_batch_used() directly.
* ilo: simplify ilo_cp_set_owner()Chia-I Wu2014-09-195-129/+121
| | | | | | The simplification allows us to get rid of ilo_cp_set_ring() and ilo_cp_implicit_flush(). The 3D query code is refactored for the simplification.
* vc4: Add support for stencil operations.Eric Anholt2014-09-188-2/+118
| | | | | | | While depth test state is passed through the fragment shader as sideband, data, the stencil test state has to be set by the fragment shader itself. Many tests are still failing, but this gets most of hiz/ passing.
* vc4: Actually implement VC4_DEBUG=cl.Eric Anholt2014-09-184-0/+141
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* vc4: Allow copy propagation of uniforms.Eric Anholt2014-09-171-1/+15
| | | | | Fixes 12 piglit tests (and 8 more crash -> fail) from reducing register pressure.
* vc4: Make sure thread end doesn't have a uniform read.Eric Anholt2014-09-171-0/+8
| | | | Prevents regression when I start doing copy propagation on uniforms.
* vc4: Allow dead code elimination of instructions that read uniforms.Eric Anholt2014-09-171-2/+1
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* vc4: Add support for reordering the uniform stream after optimization.Eric Anholt2014-09-174-0/+87
| | | | | | This allows for introducing dead code eliminating of uniforms, copy propagation of uniforms, and instruction rescheduling between instructions that both read uniforms.
* vc4: Initialize the various qreg arrays when allocating them.Eric Anholt2014-09-171-0/+4
| | | | | | | This is particularly important for outputs, where we try to MOV the whole vec4 to the VPM, even if only 1-3 components had been set up. It might also be important for temporaries, if the shader reads components before writing them.
* vc4: Fix stray disable of the CSE pass.Eric Anholt2014-09-171-1/+0
| | | | Somehow I slipped this in with the original commit of CSE.
* vc4: Claim ARB_fbo.Eric Anholt2014-09-161-1/+3
| | | | | | | | This gets a ton of piglit working that crashes in waffle context management stuff otherwise. Actually supporting mismatched FB sizes is at best going to require some more load/store generals for color buffers, but if I can't manage to do that I'll want to just have state_tracker reject those FBOs as unsupported, rather than deny GL 2.1.
* vc4: Fix memory leaks in register allocation.Eric Anholt2014-09-161-0/+3
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* vc4: Move register allocation to a separate file.Eric Anholt2014-09-164-100/+165
| | | | | I'm going to be rewriting it all, and having it mixed up with the QIR-to-QPU opcode translation was messy.
* vc4: Add support for computed depth writes.Eric Anholt2014-09-163-2/+26
| | | | Fixes piglit glsl-1.10-fragdepth and early-z.
* vc4: Restructure depth input/output in fragment shaders.Eric Anholt2014-09-164-12/+17
| | | | | | The goal here is to have an argument for the depth write opcode so that I can do computed depth. In the process, this makes the calculations that will be emitted more obvious in the QIR.
* freedreno: add a standalone ir3_compiler binary for building TGSIIlia Mirkin2014-09-162-0/+191
| | | | | | Compiler taken from the combo old/new compiler comparer + simulator. Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno: add default .dir-locals.el for emacs settingsIlia Mirkin2014-09-161-0/+8
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* llvmpipe: fix rast debugging outputDave Airlie2014-09-161-0/+11
| | | | | | | | The triangle_32_ rast functions never made it into the debug output, confused me for a few seconds. Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* llvmpipe: Fix PIPE_FORMAT_Z32_FLOAT_S8X24_UINT handling for big-endian.Richard Sandiford2014-09-161-1/+2
| | | | | | | | | | | | | | | | | llvmpipe treats PIPE_FORMAT_Z32_FLOAT_S8X24_UINT as a bit of a special case, handling it as two 32-bit pieces rather than a single 64-bit block: /* 64bit d/s format is special already extracted 32 bits */ total_bits = format_desc->block.bits > 32 ? 32 : format_desc->block.bits; The format_desc describes the whole 64-bit block, so the z shift will be 32 for big-endian. But since we're accessing the z channel as a 32-bit value rather than a 64-bit value, we need to mask the shift with 31. Signed-off-by: Richard Sandiford <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* vc4: Bump maximum ARB program temporaries to match Intel/AMD.Eric Anholt2014-09-151-1/+1
| | | | | This query has always been useless, but we could potentially reject well-formed, runnable programs if we expose a value that's too low.
* vc4: Bump maximum uniforms count to match other drivers.Eric Anholt2014-09-151-1/+1
| | | | | | We don't have any specific limits in the hardware, just like the other GPUs, so match their behavior. Fixes minmax_gles2 and several other piglit tests relying on the specced uniform minmax values.
* vc4: Dynamically allocate the TGSI-to-qreg arrays.Eric Anholt2014-09-152-12/+44
| | | | | Fixes buffer overflows in some piglit tests (which are still failing to register allocate anyway).
* vc4: Fix memory leaks of struct qinst.Eric Anholt2014-09-154-3/+17
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* vc4: Fix memory leaks of some vc4_compile contents.Eric Anholt2014-09-152-10/+11
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* vc4: Reuse the util header instead of defining our own ARRAY_SIZE.Eric Anholt2014-09-151-2/+1
| | | | | Fixes redefinition warnings if you end up including this header before util stuff.
* ilo: clean up 3D/media functionsChia-I Wu2014-09-153-205/+188
| | | | Mostly style changes to set dw[0] directly.
* ilo: fix gen6_3DSTATE_MULTISAMPLE()Chia-I Wu2014-09-151-1/+1
| | | | There was a typo introduced by 90f4b131fccae3a950864ed9ba15eea8edce915f.
* freedreno/a3xx: 3d/array texturesRob Clark2014-09-134-7/+102
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2014-09-134-4/+22
| | | | Signed-off-by: Rob Clark <[email protected]>
* ilo: trust vertex element count moreChia-I Wu2014-09-141-3/+2
| | | | | | | | | | | We might run into ve->count == 0 and last_velement_edgeflag == true in gen6_3DSTATE_VERTEX_ELEMENTS() when the state tracker sets an invalid combination of VS and VE (does not seem to happen with st/mesa). Do not assume ve->count is positive when last_velement_edgeflag is true. Reported by Coverity. Signed-off-by: Chia-I Wu <[email protected]>
* ilo: simplify src operand gathering in disassemblerChia-I Wu2014-09-141-15/+5
| | | | | | Always initialize the operand array to point to src0, src1, and src2. Signed-off-by: Chia-I Wu <[email protected]>
* ilo: derive 3-src instructions from the opcode tableChia-I Wu2014-09-141-9/+2
| | | | | | One less switch statement to maintain. Signed-off-by: Chia-I Wu <[email protected]>
* ilo: clean up 3DPRIMITIVE functionsChia-I Wu2014-09-135-25/+24
| | | | Add ILO_PRIM_RECTANGLES to replace the rectlist bool.
* ilo: clean up 3D/media common functionsChia-I Wu2014-09-133-120/+42
| | | | | | Rename ilo_builder_batch_state_base_address() to gen6_state_base_address() for consistency and remove unused gen6_STATE_BASE_ADDRESS(). Reorder the code in gen6_PIPE_CONTROL() a bit. Finally, some mostly cosmetic changes.
* ilo: move 3D functions to ilo_builder_3d*.hChia-I Wu2014-09-139-2538/+2614
| | | | | | Move functions for the 3D pipeline to the new headers. We artificially split the functions into top (vertex processing) and bottom (pixel processing), to keep the headers at reasonable sizes.
* ilo: move media functions to ilo_builder_media.hChia-I Wu2014-09-134-173/+211
| | | | Move functions for the media pipeline to the new header.
* ilo: move GPE common functions to ilo_builder_render.hChia-I Wu2014-09-137-267/+303
| | | | Move 3D/media common functions to the new header.
* freedreno: "fix" problems with excessive flushesRob Clark2014-09-125-27/+14
| | | | | | | | | | | | | | | | | | | | | | | 4f338c9b introduced logic to trigger a flush rather than overflowing cmdstream buffer. But the threshold was too low, triggering flushes where they were not needed. This caused problems with games like xonotic. Part of the problem is that we need to mark all state dirty between cmdstream submit ioctls, because we cannot rely on state being preserved across ioctls. But even with that, there are still some problems that are still being debugged. For now: 1) correctly mark all state dirty 2) introduce FD_MESA_DEBUG flush flag to force rendering to be flushed between each draw, to trigger problems (so that I can debug) 3) use a more reasonable threshold so for normal usecases we don't trigger the problems This at least corrects the regression, but there is still more debugging to do. Signed-off-by: Rob Clark <[email protected]>
* r600g,radeonsi: add debug option which forces DMA for copy_region and blitMarek Olšák2014-09-1211-21/+52
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* freedreno/ir3: implement UMUL correctlyIlia Mirkin2014-09-121-1/+48
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix UCMP handlingIlia Mirkin2014-09-121-37/+39
| | | | | | | UCMP does not require a compare, only a select. Signed-off-by: Ilia Mirkin <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: add TXL supportIlia Mirkin2014-09-121-1/+3
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Signed-off-by: Rob Clark <[email protected]>
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