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* gallium/ddebug: Add passthrough for get_compute_param.Bas Nieuwenhuizen2016-05-131-0/+12
* nvc0: fix indentation in nvc0_invalidate_resource_storage()Samuel Pitoiset2016-05-121-52/+52
* nvc0: save some CPU cycles in nvc0_context_unreference_resources()Samuel Pitoiset2016-05-121-8/+6
* nvc0: invalidate texture buffers for computeSamuel Pitoiset2016-05-121-3/+8
* swr: properly expose compressed format supportTim Rowley2016-05-121-0/+17
* nvc0: fix gl_SampleMaskIn computationIlia Mirkin2016-05-1110-5/+94
* nv50/ir: generalize interp fixups to be able to fixup anythingIlia Mirkin2016-05-1110-60/+71
* nir/algebraic: Separate ffma lowering from fusingJason Ekstrand2016-05-111-0/+1
* freedreno: fix multi-layer transfer_map'sRob Clark2016-05-111-1/+1
* swr: [rasterizer] Include cmath for std::isnan and std::isinf.Vinson Lee2016-05-101-0/+2
* radeonsi: Set declared tessellation LDS size to hardware size.Bas Nieuwenhuizen2016-05-101-16/+2
* freedreno/ir3: size input/output arrays properlyRob Clark2016-05-101-3/+14
* nvc0: enable compute support by default on GK110+Samuel Pitoiset2016-05-101-15/+3
* gallium/radeon: don't flush the GFX IB if DMA doesn't depend on itMarek Olšák2016-05-101-2/+8
* radeonsi: consolidate radeon_add_to_buffer_list calls for DMAMarek Olšák2016-05-103-33/+14
* gallium/radeon: add a heuristic for better (S)DMA performanceMarek Olšák2016-05-102-0/+16
* gallium/radeon: flush if DMA IB memory usage is too highMarek Olšák2016-05-108-15/+35
* radeonsi: add new SDMA texture copy codeMarek Olšák2016-05-101-0/+438
* gallium/radeon: fix (S)DMA read-after-write hazardsMarek Olšák2016-05-108-0/+32
* radeonsi: raise the max size for SDMA buffer copiesMarek Olšák2016-05-102-3/+3
* radeonsi: remove SDMA texture copy codeMarek Olšák2016-05-101-215/+2
* radeonsi: only expose *_init_*dma_functions from (S)DMA filesMarek Olšák2016-05-105-34/+31
* gallium/radeon: implement randomized SDMA texture copy testing (v2)Marek Olšák2016-05-106-0/+419
* gallium/radeon: discard CMASK or DCC if overwriting a whole texture by DMAMarek Olšák2016-05-101-7/+39
* gallium/radeon: use a common function for DMA blit preparationMarek Olšák2016-05-106-31/+73
* gallium/radeon: split out code for discarding DCCMarek Olšák2016-05-101-6/+12
* gallium/radeon: rename r600_texture_disable_cmask -> discard_cmaskMarek Olšák2016-05-101-2/+2
* gallium/radeon: fix partial layered transfers of cube (array) texturesMarek Olšák2016-05-101-15/+6
* gallium/radeon: use gart_page_size instead of hardcoded 4096Marek Olšák2016-05-104-6/+13
* winsys/amdgpu: move gart_page_size to struct radeon_winsysMarek Olšák2016-05-101-0/+1
* freedreno/ir3: lower lrp when operating with double operandsSamuel Iglesias Gonsálvez2016-05-101-0/+1
* nv50/ir: silence unsupported TGSI_PROPERTY_CS_FIXED_BLOCK_*Samuel Pitoiset2016-05-091-0/+5
* freedreno/ir3: fix fallout from new block iteratorsRob Clark2016-05-091-1/+1
* radeonsi: workaround for tesselation on SINicolai Hähnle2016-05-091-0/+8
* radeonsi: always allocate export memory for pixel shadersNicolai Hähnle2016-05-091-5/+10
* radeonsi: expose performance counters as 64 bitNicolai Hähnle2016-05-092-16/+19
* swr: Add missing break in query switch statement.Bruce Cherniak2016-05-091-0/+1
* freedreno/ir3: allow for additional VS sysval inputsRob Clark2016-05-091-2/+5
* r300g: add support for PIPE_FORMAT_x8R8G8B8_*Marek Olšák2016-05-092-15/+77
* radeonsi: fix undefined behavior (memcpy arguments must be non-NULL)Nicolai Hähnle2016-05-071-1/+3
* radeonsi: fix some reported undefined left-shiftsNicolai Hähnle2016-05-071-3/+3
* gallium/radeon: clean left-shift undefined behaviorNicolai Hähnle2016-05-0711-3989/+3989
* gallium: fix various undefined left shifts into sign bitNicolai Hähnle2016-05-071-2/+2
* radeonsi: Compute correct LDS size for fragment shaders.Bas Nieuwenhuizen2016-05-061-3/+6
* vc4: Add support for loading immediate values in QIR.Eric Anholt2016-05-064-0/+32
* vc4: Make vc4_qpu_validate() produce more verbose failures.Eric Anholt2016-05-061-35/+71
* vc4: Add a small QIR validate pass.Eric Anholt2016-05-064-0/+127
* vc4: Fix the src count on exp2/log2.Eric Anholt2016-05-061-2/+2
* vc4: Reuse QPU disasm's cond flags in QIR.Eric Anholt2016-05-063-27/+46
* vc4: When emitting an instruction to an existing temp, mark it non-SSA.Eric Anholt2016-05-061-0/+2
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