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* gallium: Add PIPE_CAP_ENDIANNESSTom Stellard2013-07-2212-0/+25
| | | | | | Cc: [email protected] [ Francisco Jerez: Fix "PIPE_ENDIAN_SMALL" in the documentation, define PIPE_ENDIAN_NATIVE. ]
* llvmpipe: Ensure FTZ/DAZ flags are set on deferred draw flushes.Zack Rusin2013-07-221-0/+8
| | | | Tested-by: José Fonseca <[email protected]>
* llvmpipe: Remove lp_rast_get_num_threads().José Fonseca2013-07-222-11/+0
| | | | | | Never called. Trivial.
* llvmpipe/tests: update arith test to check for edge casesZack Rusin2013-07-191-9/+19
| | | | | | | | | Test infs, zeros and nans with our arith functions to assure correct/defined behavior with those values. Signed-off-by: Zack Rusin <[email protected]> Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* llvmpipe: clamp inputs for srgb render buffersRoland Scheidegger2013-07-181-0/+35
| | | | | | | | | | | | | | | Usually with fixed point renderbuffers clamping is done as part of conversion. However, since we blend in float format, we essentially skip all conversion steps pre-blend but since this is still a fixed point renderbuffer we must still clamp the inputs in this case. Makes no difference for piglit though. Obviously we could skip this if fragment color clamping is enabled, but a) this is deprecated in OpenGL (d3d never had it) and b) we don't support it natively so it gets baked into the shader. Also add some comment about logic ops being broken for srgb, luckily no test tries to do that as there's no easy fix... Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Zack Rusin <[email protected]>
* llvmpipe: fix blending with SRC_ALPHA_SATURATE with some formats without alphaRoland Scheidegger2013-07-182-8/+26
| | | | | | | | | | | | | | | | | | We were fixing up the blend factor to ZERO, however this only works correctly with fixed point render buffers where the input values are clamped to 0/1 (because src_alpha_saturate is min(As, 1-Ad) so can be negative with unclamped inputs). Haven't seen any failure anywhere due to that with fixed point SNORM buffers (which clamp inputs to -1/1) but it should apply there as well (snorm blending is rare, even opengl 4.3 doesn't require snorm rendertargets at all, d3d10 requires them but they are not blendable). Doesn't look like piglit hits this though (some internal testing hits the float case at least). (With legacy OpenGL we could theoretically still use the fixup to zero if the fragment color clamp is enabled, but we can't detect that easily since we don't support native clamping hence it gets baked into the shader.) Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Zack Rusin <[email protected]>
* r600g: use WAIT_3D_IDLE before using CP DMAMarek Olšák2013-07-182-0/+2
| | | | I broke this with 7948ed1250cae78ae1b22dbce4ab23aceacc6159 for r700 at least.
* r300g: make use of gallium's os_get_process_name()Jonathan Gray2013-07-181-1/+6
| | | | | | | Lets the code compile on non Linux systems. Signed-off-by: Jonathan Gray <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* nv50: H.264/MPEG2 decoding support via VP2, available on NV84-NV96, NVA0Ilia Mirkin2013-07-1811-3/+1815
| | | | | | | | | | | | | | Adds H.264 and MPEG2 codec support via VP2, using firmware from the blob. Acceleration is supported at the bitstream level for H.264 and IDCT level for MPEG2. Known issues: - H.264 interlaced doesn't render properly - H.264 shows very occasional artifacts on a small fraction of videos - MPEG2 + VDPAU shows frequent but small artifacts, which aren't there when using XvMC on the same videos Signed-off-by: Ilia Mirkin <[email protected]>
* r600g/sb: improve alu packing on caymanVadim Girlin2013-07-172-15/+89
| | | | | | | | | | | | | | | | Scheduler/register allocator in r600-sb was developed and optimized on evergreen (VLIW-5) hardware, so currently it's not optimal for VLIW-4 chips. This patch should improve performance on cayman gpus due to better alu packing, but also it tends to increase register usage, so overall positive effect on performance has to be proven by real benchmarks yet. Some results with bfgminer kernel on cayman: source bytecode: 60 gprs, 3905 alu groups, sbcl before the patch: 45 gprs, 4088 alu groups, sbcl with this patch: 55 gprs, 3474 alu groups. Signed-off-by: Vadim Girlin <[email protected]>
* r600g/sb: fix handling of new multislot instructions on caymanVadim Girlin2013-07-173-5/+6
| | | | | | | Ex-scalar instructions that became multislot on cayman do replicate result to all channels - handle them similar to DOT4. Signed-off-by: Vadim Girlin <[email protected]>
* r600g/sb: fix debug dump code in schedulerVadim Girlin2013-07-171-4/+5
| | | | | | Update the stale debug code for other changes related to debug output. Signed-off-by: Vadim Girlin <[email protected]>
* r600g/sb: fix initial register allocationVadim Girlin2013-07-171-0/+1
| | | | | | | | | | Mark values that are members of the 'same register' constraint as preallocated in ra_init pass, this will prevent incorrect reallocation in scheduler in some cases. Should fix https://bugs.freedesktop.org/show_bug.cgi?id=66713 Signed-off-by: Vadim Girlin <[email protected]>
* r600g/sb: move chip & class name functions to sb_contextVadim Girlin2013-07-174-53/+55
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* r600g/sb: fix handling of PS in source bytecode on caymanVadim Girlin2013-07-171-0/+5
| | | | | | | | | Actually PS doesn't make sense for cayman and isn't even mentioned in cayman docs, but llvm backend currently uses it in bytecode and, assuming that hw seems to be mostly ok with it, this will allow sb to parse such source bytecode correctly. Signed-off-by: Vadim Girlin <[email protected]>
* r600g/sb: Initialize ra_checker member variables.Vinson Lee2013-07-171-1/+1
| | | | | | Fixes "Uninitialized scalar field" defect reported by Coverity. Signed-off-by: Vinson Lee <[email protected]>
* llvmpipe: support sRGB framebuffersRoland Scheidegger2013-07-162-14/+57
| | | | | | | | | | | | | | | Just use the new conversion functions to do the work. The way it's plugged in into the blend code is quite hacktastic but follows all the same hacks as used by packed float format already. Only support 4x8bit srgb formats (rgba/rgbx plus swizzle), 24bit formats never worked anyway in the blend code and are thus disabled, and I don't think anyone is interested in L8/L8A8. Would need even more hacks otherwise. Unless I'm missing something, this is the last feature except MSAA needed for OpenGL 3.0, and for OpenGL 3.1 as well I believe. v2: prettify a bit, use separate function for packing. Reviewed-by: Jose Fonseca <[email protected]>
* Revert "r300g: allow HiZ with a 16-bit zbuffer"Marek Olšák2013-07-151-0/+1
| | | | | | | | This reverts commit 631c631cbf5b7e84e42a7cfffa1c206d63143370. https://bugs.freedesktop.org/show_bug.cgi?id=66921 Cc: [email protected]
* r300g/swtcl: fix a lockup in MSAA resolveMarek Olšák2013-07-151-0/+7
| | | | Cc: [email protected]
* r300g/swtcl: fix geometry corruption by uploading indices to a bufferMarek Olšák2013-07-153-45/+31
| | | | | | | | | | | | | The splitting of a draw call into several draw commands was broken, because the split sometimes took place in the middle of a primitive. The splitting was supposed to be dealing with the case when there are more indices than the maximum size of a CS. This commit throws that code away and uses a real index buffer instead. https://bugs.freedesktop.org/show_bug.cgi?id=66558 Cc: [email protected]
* ilo: skip 3DSTATE_INDEX_BUFFER when possibleChia-I Wu2013-07-144-59/+77
| | | | | | When only the offset to the index buffer is changed, we can skip the 3DSTATE_INDEX_BUFFER if we always use 0 for the offset, and add (offset / index_size) to Start Vertex Location in 3DPRIMITIVE.
* r600g/sb: Initialize ra_constraint::cost.Vinson Lee2013-07-131-1/+1
| | | | | | Fixes "Uninitialized scalar field" reported by Coverity. Signed-off-by: Vinson Lee <[email protected]>
* ilo: move a santiy check into its assert()Chia-I Wu2013-07-131-5/+2
| | | | | | The compiler does not know that ilo_3d_pipeline_estimate_size() is pure and can be eliminated in a release build in gen6_pipeline_end(). Move the call into the assert().
* ilo: mark some states dirty when they are really changedChia-I Wu2013-07-131-0/+16
| | | | | The checks may seem redundant because cso_context handles them, but util_blitter does not have access to cso_context.
* ilo: clean up ilo_blitter_pipe_begin()Chia-I Wu2013-07-133-27/+39
| | | | | Document why certain states need to be saved, and fix a bug when blitting with scissor enabled.
* r600g: don't use the CB/DB CP COHER logic on r6xxAlex Deucher2013-07-121-2/+10
| | | | | | | | | There are hw bugs. Flush and inv event is sufficient. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=66837 Signed-off-by: Alex Deucher <[email protected]>
* nv30: fix KILL_IF breakageBrian Paul2013-07-121-1/+1
| | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=66858
* tgsi: rename the TGSI fragment kill opcodesBrian Paul2013-07-1214-55/+53
| | | | | | | | | | | | | | | | | | | | | TGSI_OPCODE_KIL and KILP had confusing names. The former was conditional kill (if any src component < 0). The later was unconditional kill. At one time KILP was supposed to work with NV-style condition codes/predicates but we never had that in TGSI. This patch renames both opcodes: TGSI_OPCODE_KIL -> KILL_IF (kill if src.xyzw < 0) TGSI_OPCODE_KILP -> KILL (unconditional kill) Note: I didn't just transpose the opcode names to help ensure that I didn't miss updating any code anywhere. I believe I've updated all the relevant code and comments but I'm not 100% sure that some drivers had this right in the first place. For example, the radeon driver might have llvm.AMDGPU.kill and llvm.AMDGPU.kilp mixed up. Driver authors should review their code. Reviewed-by: Jose Fonseca <[email protected]>
* softpipe: silence some MSVC warningsBrian Paul2013-07-122-14/+14
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* radeon/uvd: fall back to shader based decoding for MPEG2 on UVD 2.x v2Christian König2013-07-122-5/+19
| | | | | | | | | | | UVD 2.x doesn't support hardware decoding of MPEG2, just use shader based decoding for those chipsets. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=66450 v2: fix interlacing as well Signed-off-by: Christian König <[email protected]>
* r600g: x/y coordinates must be divided by block dim in dma blitChristoph Bumiller2013-07-112-4/+16
| | | | | | | Note: this is a candidate for the 9.1 branch. Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* r600g/sb: Fix Android build v2Chih-Wei Huang2013-07-124-7/+8
| | | | | | | Add the sb CXX files to the Android Makefile and also stop using some c++11 features. v2 (Vadim Girlin): use &bc[0] instead of bc.begin()
* r600g/sb: improve math optimizations v2Vadim Girlin2013-07-1111-47/+435
| | | | | | | | | | | | | | | | This patch adds support for some math optimizations that are generally considered unsafe, that's why they are currently disabled for compute shaders. GL requirements are less strict, so they are enabled for for GL shaders by default. In case of any issues with applications that rely on higher precision than guaranteed by GL, 'sbsafemath' option in R600_DEBUG allows to disable them. v2 - always set proper src vector size for transformed instructions - check for clamp modifier in the expr_handler::fold_assoc Signed-off-by: Vadim Girlin <[email protected]>
* ilo: reduce PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS to 12Chia-I Wu2013-07-111-2/+3
| | | | So that there are at most (2^22 * 6) texels, lower than the 2^26 limit.
* ilo: correctly initialize undefined registers in fsChia-I Wu2013-07-111-5/+15
| | | | | Initialize all 4 channels of undefined registers (that is, TEMPs that are used before being assigned) in FS.
* radeonsi: Handle TGSI_OPCODE_DDX/Y using local memoryMichel Dänzer2013-07-104-2/+103
| | | | | | 16 more little piglits. Reviewed-by: Tom Stellard <[email protected]>
* radeonsi: Handle TGSI_OPCODE_TXDMichel Dänzer2013-07-101-2/+25
| | | | | | One more little piglit. Reviewed-by: Tom Stellard <[email protected]>
* ilo: honor surface padding requirementsChia-I Wu2013-07-101-0/+53
| | | | The PRM specifies several padding requirements that we failed to honor.
* util: treat denorm'ed floats like zeroZack Rusin2013-07-092-0/+11
| | | | | | | | | | | | | The D3D10 spec is very explicit about treatment of denorm floats and the behavior is exactly the same for them as it would be for -0 or +0. This makes our shading code match that behavior, since OpenGL doesn't care and on a few cpu's it's faster (worst case the same). Float16 conversions will likely break but we'll fix them in a follow up commit. Signed-off-by: Zack Rusin <[email protected]> Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* r600g: improve the mechanism for recognizing an empty CSMarek Olšák2013-07-083-3/+8
| | | | Reviewed-by: Alex Deucher <[email protected]>
* r600g: explicitly flush caches for streamout-based buffer copying & clearingMarek Olšák2013-07-081-0/+13
| | | | | | | It's done automatically for vertex buffers, but not for constant buffers, textures, and colorbuffers. Reviewed-by: Alex Deucher <[email protected]>
* r600g: only flush the caches that need to be flushed during CP DMA operationsMarek Olšák2013-07-083-32/+117
| | | | | | | This should increase performance if constant uploads are done with the CP DMA, because only the cache that needs to be flushed is flushed. Reviewed-by: Alex Deucher <[email protected]>
* r600g: split INVAL_READ_CACHES into vertex, tex, and const cache flagsMarek Olšák2013-07-085-27/+52
| | | | | | | also flushing any cache in evergreen_emit_cs_shader seems to be superfluous (we don't flush caches when changing the other shaders either) Reviewed-by: Alex Deucher <[email protected]>
* r600g: adjust flush flags (v3)Alex Deucher2013-07-086-7/+42
| | | | | | | | | | | | | 1. flush SH with read caches 2. add flag for DB flushes 3. add flag for CB flushes v2: flush all CBs, remove redundant emit_state variable. v3: Marek: also set the new flags in r600_context_flush, the CP dma functions, and texture_barrier, and rename them Signed-off-by: Marek Olšák <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600g: don't call buffer_wait in buffer_mmap_sync_with_ringsMarek Olšák2013-07-081-2/+1
| | | | | | | | The winsys should do this, because it measures how much time we spend in buffer_map doing synchronization, which can be viewed with the gallium HUD. Reviewed-by: Alex Deucher <[email protected]>
* r600g: don't read back the MSAA depth buffer if the read flag is not setMarek Olšák2013-07-081-8/+8
| | | | Reviewed-by: Alex Deucher <[email protected]>
* r600g: don't flush the context in texture_transfer_mapMarek Olšák2013-07-081-5/+0
| | | | | | the winsys does this automatically Reviewed-by: Alex Deucher <[email protected]>
* r600g: fix texture offset computation for mapped MSAA depth buffersMarek Olšák2013-07-082-16/+14
| | | | | | | | | It was wrong, because the offset shouldn't be applied to MSAA depth buffers. This small cleanup should prevent such issues in the future. This fixes a lockup in "piglit/fbo-depthstencil default_fb -samples=n". Reviewed-by: Alex Deucher <[email protected]>
* r600g: fix color resolve for RGBX8 and RGBX16 integer formatsMarek Olšák2013-07-081-2/+2
| | | | Reviewed-by: Alex Deucher <[email protected]>
* r600g: enable fast MSAA color clear for array/3D/cube texturesMarek Olšák2013-07-081-4/+3
| | | | Reviewed-by: Alex Deucher <[email protected]>
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