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* broadcom/vc5: Enable the driver on V3D 4.1Eric Anholt2018-01-121-1/+1
* broadcom/vc5: Port the simulator to support V3D 4.1Eric Anholt2018-01-129-125/+216
* broadcom/vc5: Port the RCL setup to V3D4.1.Eric Anholt2018-01-127-58/+360
* broadcom/vc5: Fix per-tile extra clear packet.Eric Anholt2018-01-121-1/+1
* broadcom/vc5: Move the TLB loads and stores to helper functions.Eric Anholt2018-01-121-35/+50
* broadcom/vc5: Convert vc5_cl.h to use the V3DX() macros.Eric Anholt2018-01-127-10/+24
* meson: move libsensors dependency to libgalliumDylan Baker2018-01-114-6/+3
* meson: Use dependencies for nirDylan Baker2018-01-114-13/+15
* meson: Use consistent style for testsDylan Baker2018-01-112-2/+6
* meson: Use consistent styleDylan Baker2018-01-111-2/+4
* svga: simplify failure code in emit_rss_vgpu9()Brian Paul2018-01-111-17/+12
* svga: remove unused fail parameter to EMIT_RS(), EMIT_RS_FLOAT()Brian Paul2018-01-111-57/+57
* svga: add assertion in svga_queue_rs()Brian Paul2018-01-111-0/+1
* svga: whitespace/formatting fixes in svga_state_rss.cBrian Paul2018-01-111-79/+75
* ac: add load_patch_vertices_in() to the abiTimothy Arceri2018-01-111-6/+14
* swr: Handle indirect indices in GSGeorge Kyriazis2018-01-101-8/+39
* amd/common: import get_{load,store}_intr_attribs() from RadeonSISamuel Pitoiset2018-01-101-21/+5
* swr/rast: switch win32 jit format to COFFTim Rowley2018-01-101-2/+2
* swr/rast: don't use 32-bit gathers for elements < 32-bits in sizeTim Rowley2018-01-101-1/+60
* swr/rast: autogenerate named structs instead of literal structsTim Rowley2018-01-101-8/+15
* swr/rast: SIMD16 fetch shader jitter cleanupTim Rowley2018-01-101-720/+368
* swr/rast: shuffle header files for msvc pre-compiled header usageTim Rowley2018-01-1010-88/+143
* swr/rast: SIMD16 builder - cleanup naming (simd2 -> simd16)Tim Rowley2018-01-105-233/+239
* r600: don't emit tes samplers/views when tes isn't activeRoland Scheidegger2018-01-102-0/+19
* r600: increase number of UBOs to 15Roland Scheidegger2018-01-103-22/+37
* r600: use GET_BUFFER_RESINFO vtx fetch on eg instead of setting up constsRoland Scheidegger2018-01-104-58/+50
* r600: increase number of ubos by one to 14Roland Scheidegger2018-01-104-4/+9
* r600: set up constants needed for txq for buffers and cube maps with tesRoland Scheidegger2018-01-101-0/+16
* r600: don't emit reloc for ring buffer out into the blueRoland Scheidegger2018-01-102-8/+6
* r600: hack up num_render_backends on Juniper to 8Roland Scheidegger2018-01-101-2/+19
* r600: fix enabled_rb_mask on eg/cmRoland Scheidegger2018-01-101-2/+9
* r600: fix sampler indexing with texture buffers samplingRoland Scheidegger2018-01-102-2/+4
* r600: don't use vtx offset for load_sample_positionRoland Scheidegger2018-01-101-1/+1
* r600: drop l2 related queriesDave Airlie2018-01-103-18/+0
* r600/shader: only read back the necessary tess factor components.Dave Airlie2018-01-101-4/+4
* meson: set opencl flags for r600Dylan Baker2018-01-081-2/+5
* meson: Build SWR driverDylan Baker2018-01-082-0/+447
* ac: add load_tess_level() to the abiTimothy Arceri2018-01-091-0/+22
* radeonsi: add load_tess_level() helperTimothy Arceri2018-01-091-14/+19
* nvc0: enable bindless on keplerIlia Mirkin2018-01-071-3/+3
* nvc0: add bindless image support for keplerIlia Mirkin2018-01-0711-75/+272
* nvc0: add support for bindless textures on kepler+Ilia Mirkin2018-01-0710-5/+183
* nv50/ir: use the image info in the instruction rather than declIlia Mirkin2018-01-071-52/+24
* nvc0/ir: safen up lowering logic against overwriting reused valuesIlia Mirkin2018-01-071-2/+4
* nvc0: update tic in-place when buffer address changesIlia Mirkin2018-01-072-14/+21
* nvc0: ensure that pushbuf keeps ref to old text/tls bosIlia Mirkin2018-01-071-0/+13
* st/glsl_to_nir/radeonsi: enable tessellation shadersTimothy Arceri2018-01-051-0/+2
* radeonsi: add dummy implementation of si_nir_scan_tess_ctrl()Timothy Arceri2018-01-053-0/+23
* ac/radeonsi: add load_tess_coord() to the abiTimothy Arceri2018-01-051-17/+25
* radeonsi: make si_llvm_emit_tcs_epilogue compatible with emit_outputs abiTimothy Arceri2018-01-051-3/+7
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