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* freedreno/a5xx: correct image/ssbo offsetRob Clark2018-06-111-1/+1
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: use saml always if we have lodRob Clark2018-06-111-1/+1
| | | | | | | In some cases we get plain tex opcodes (but w/ a lod argument).. in this case always use the saml instruction. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: don't cp absneg into meta:fiRob Clark2018-06-111-0/+4
| | | | | | | | | | | If using a fanin (collect) to collect of consecutive registers together, we can CP mov's into the fanin, but not (abs) or (neg). No places that allow those modifiers are consuming a fanin anyways. But this caused an absneg to be lost between a ldgb and stgb for shaders like: outputs[n] = abs(input[n]) Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: rework size/type conversion instructionsRob Clark2018-06-111-10/+156
| | | | | | With 8b and 16b, there are a lot more to handle. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: propagate HALF flag across fanoutRob Clark2018-06-111-1/+4
| | | | | | | | | | If we have a fanout (split) meta instruction to split the result of a vector instruction, propagate the HALF flag back to the original instruction. Otherwise result ends up in a full precision register while instruction(s) that use the result look in a half-precision register. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: add sample-id/sample-mask-inRob Clark2018-06-111-3/+12
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: add sample-id/sample-mask-inRob Clark2018-06-111-0/+21
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2018-06-118-87/+213
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: image atomics use image-store pathRob Clark2018-06-111-0/+8
| | | | | | | | image reads are handled via tex state, whereas image writes and atomics are handled via SSBO state block. Previously we were only considering image write, and not image atomics which also uses the SSBO state block. Signed-off-by: Rob Clark <[email protected]>
* virgl: enable ARB_gpu_shader_fp64Dave Airlie2018-06-111-1/+2
| | | | | | | This enables ARB_gpu_shader_fp64 if the host provides it. Tested-by: Gurchetan Singh <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* radeonsi: emit_dpbb_state packets optimizationSonny Jiang2018-06-072-21/+26
| | | | | | | Remembering latest states of registers to eliminate redunant SET_CONTEXT_REG packets Signed-off-by: Sonny Jiang <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* radeonsi: emit_clip_state packets optimizationSonny Jiang2018-06-072-3/+7
| | | | | | | Remembering latest states of registers to eliminate redunant SET_CONTEXT_REG packets Signed-off-by: Sonny Jiang <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* radeonsi: emit_msaa_sample_locs packets optimizationSonny Jiang2018-06-072-2/+6
| | | | | | | Remembering latest states of registers to eliminate redunant SET_CONTEXT_REG packets Signed-off-by: Sonny Jiang <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* radeonsi: emit_msaa_config packets optimizationSonny Jiang2018-06-072-28/+28
| | | | | | | Remembering latest states of registers to eliminate redunant SET_CONTEXT_REG packets Signed-off-by: Sonny Jiang <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* radeonsi: emit_cb_render_state packets optimizationSonny Jiang2018-06-073-9/+48
| | | | | | | Remembering latest states of registers to eliminate redunant SET_CONTEXT_REG packets Signed-off-by: Sonny Jiang <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* radeonsi: emit_db_render_state packets optimizationSonny Jiang2018-06-075-29/+95
| | | | | | | Remembering latest states of registers to eliminate redunant SET_CONTEXT_REG packets Signed-off-by: Sonny Jiang <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* radeonsi: fix possible truncation on renderer stringTimothy Arceri2018-06-081-1/+1
| | | | | | | Fixes truncation warning in gcc 8.1 Fixes: 8539c9bf3158 ("gallium/radeon: add the kernel version into the renderer string") Reviewed-by: Michel Dänzer <[email protected]>
* v3d: Work around GFXH-1461/GFXH-1689 by using CLEAR_TILE_BUFFERS.Eric Anholt2018-06-061-10/+17
| | | | | | | This doesn't seem to have done anything to my test results. However, given that we've still got a class of GPU hangs, following the workarounds that the closed driver does so that we get the same command sequences seems like a good idea.
* r300g/swtcl: make pipe_context uploaders use malloc'd memory as beforeMarek Olšák2018-06-051-3/+6
| | | | | | | | | | Discovered by Roland Scheidegger. The resource_create code uses GPU memory for PIPE_BIND_CUSTOM, but malloc'd memory otherwise. Vertex and index buffers should use malloc'd memory. Cc: 18.0 18.1 <[email protected]>
* v3d: Be more explicit about include directory from our generated code.Eric Anholt2018-06-052-1/+4
| | | | | | | You'd need src/broadcom/cle/ in the -I previously, for srcdir != builddir. nir was fine at that, but automake didn't have it. Bugzilla: https://github.com/anholt/mesa/issues/104
* virgl: use bits in caps set v2[email protected]2018-06-052-0/+6
| | | | | | | | | Let's add another field to caps v2, that can help report boolean values. Suggested-by: Gert Wollny <[email protected]> Suggested-by: Dave Airlie <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* virgl: add shader offset alignment to to v2 caps struct[email protected]2018-06-053-1/+4
| | | | | | | | | | | | | | | | | | This is the SSBO analogue to fe0647. User supplied data must be a multiple of GL_SHADER_STORAGE_BUFFER_OFFSET_ALIGNMENT. This fixes 44 GLES31 tests on airlied@'s GLES31 sketch branches with Nvidia hardware, but this patch standalone can applied to master. The alignment restriction on Nvidia is 32, hence the default value. Example tests: dEQP-GLES31.functional.ssbo.layout.random.all_shared_buffer.0 dEQP-GLES31.functional.ssbo.layout.multi_basic_types.single_buffer.std430 v2: Move to a better place in case statement v3: Rebase Reviewed-by: Dave Airlie <[email protected]>
* virgl: Always assume that ORIGIN_UPPER_LEFT and PIXEL_CENTER* are supportedGert Wollny2018-06-011-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver must support at least one of PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT and one of PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER otherwise glsl_to_tgsi will fire an assert. ORIGIN_UPPER_LEFT is the default convention, and is supported by all mesa drivers, hence it seems reasonable to always report the caps to be enabled. On gles ORIGIN_LOWER_LEFT is generally not supported, so we rely on the caps reported by the host that depend on whether we run on an GL or an EGL host. For PIXEL_CENTER it is completely host driver dependend on what is supported, and since we do not report the actual host driver capabilities it is best to mark both as supported, this is how it works for a GL host too. Fixes: dEQP-GLES3.functional.shaders.builtin_variable.fragcoord_xyz dEQP-GLES3.functional.shaders.metamorphic.bubblesort_flag.variant_1 dEQP-GLES3.functional.shaders.metamorphic.bubblesort_flag.variant_2 Reviewed-by: Gurchetan Singh <[email protected]> Signed-off-by: Gert Wollny <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* radeonsi: Fix crash on shaders using MSAA image load/storeAlex Smith2018-06-011-1/+7
| | | | | | | | | | | | The value returned by tgsi_util_get_texture_coord_dim() does not account for the sample index. This means image_fetch_coords() will not fetch it, leading to a null deref in ac_build_image_opcode() which expects it to be present (the return value of ac_num_coords() *does* include the sample index). Signed-off-by: Alex Smith <[email protected]> Cc: "18.1" <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* v3d: Fix automake linking error.Vinson Lee2018-05-301-1/+3
| | | | | | | | | | | | | CXXLD gallium_dri.la ../../../../src/broadcom/.libs/libbroadcom.a(clif_dump.o): In function `clif_dump_packet': src/broadcom/clif/clif_dump.c:87: undefined reference to `v3d33_clif_dump_packet' src/broadcom/clif/clif_dump.c:85: undefined reference to `v3d41_clif_dump_packet' ../../../../src/broadcom/.libs/libbroadcom.a(clif_dump.o): In function `clif_process_worklist': src/broadcom/clif/clif_dump.c:140: undefined reference to `v3d41_clif_dump_gl_shader_state_record' src/broadcom/clif/clif_dump.c:144: undefined reference to `v3d33_clif_dump_gl_shader_state_record' Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* virgl: Update virgl_hw.hJakob Bornecrantz2018-05-301-0/+1
| | | | | | Reviewed-by: Gurchetan Singh <[email protected]> Reviewed-by: Dave Airlie <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* virgl: add ARB_transform_feedback_overflow_query supportDave Airlie2018-05-302-2/+4
| | | | | Reviewed-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* virgl: add polygon offset clampDave Airlie2018-05-301-1/+2
| | | | | Reviewed-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* virgl: add derivative control supportDave Airlie2018-05-301-1/+2
| | | | | Reviewed-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* virgl: add ARB_conditional_render_inverted supportDave Airlie2018-05-301-1/+2
| | | | | Reviewed-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* virgl: update caps bitset to latest version.Dave Airlie2018-05-301-0/+5
| | | | | | | | This makes this use all 32 bits, so future sets need to be defined in a new struct. Reviewed-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* nv30: add a couple of missed shader capsIlia Mirkin2018-05-301-0/+2
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nv30: ensure that displayable formats are marked accordinglyIlia Mirkin2018-05-301-4/+6
| | | | | | Fixes: f7604d8af52 ("st/dri: only expose config formats that are display targets") Cc: "18.1" <[email protected]> Signed-off-by: Ilia Mirkin <[email protected]>
* gallium: add PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITYMarek Olšák2018-05-2916-0/+30
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* gallium/winsys: rename DRM_API_HANDLE_* to WINSYS_HANDLE_*Dave Airlie2018-05-308-31/+31
| | | | | | | | | | | | This just renames this as we want to add an shm handle which isn't really drm related. Originally by: Marc-André Lureau <[email protected]> (airlied: I used this sed script instead) This was generated with: git grep -l 'DRM_API_' | xargs sed -i 's/DRM_API_/WINSYS_/g' Reviewed-by: Marek Olšák <[email protected]>
* tegra: Treat resources with modifiers as scanoutThierry Reding2018-05-291-1/+12
| | | | | | | | | | | | | | | Resources created with modifiers are treated as scanout because there is no way for applications to specify the usage (though that capability may be useful to have in the future). Currently all the resources created by applications with modifiers are for scanout, so make sure they have bind flags set accordingly. This is necessary in order to properly export buffers for such resources so that they can be shared with scanout hardware. Tested-by: Daniel Kolesa <[email protected]> Cc: [email protected] Signed-off-by: Thierry Reding <[email protected]>
* tegra: Fix scanout resources without modifiersThierry Reding2018-05-291-1/+18
| | | | | | | | | | | | Resources created for scanout but without modifiers need to be treated as pitch-linear. This is because applications that don't use modifiers to create resources must be assumed to not understand modifiers and in turn won't be able to create a DRM framebuffer and passing along which modifiers were picked by the implementation. Tested-by: Daniel Kolesa <[email protected]> Cc: [email protected] Signed-off-by: Thierry Reding <[email protected]>
* tegra: Remove usage of non-stable UAPIThierry Reding2018-05-291-66/+3
| | | | | | | | This code path is no longer required with framebuffer modifier support. Tested-by: Daniel Kolesa <[email protected]> Cc: [email protected] Signed-off-by: Thierry Reding <[email protected]>
* nv50/ir: Extend ImmediateValue::applyLog2 to 64-bit integersPierre Moreau2018-05-291-1/+10
| | | | | | Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Karol Herbst <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* gm107/ir: prevent WaW hazards in instruction schedulingRhys Perry2018-05-281-54/+57
| | | | | | | | Previously, findFirstUse() only considered reads "uses". This fixes that by making it check both an instruction's sources and definitions. It also shortens both findFistUse() and findFirstDef() along the way. Reviewed-by: Ilia Mirkin <[email protected]>
* r600: Fix SSG when not all components are writtenGert Wollny2018-05-281-4/+10
| | | | | | | | | | | | | | | | | | | | | Make sure only those components are written to that are specified in the write mask. Fixes: dEQP-GLES2.functional.shaders.operator.common_functions.sign.lowp_float_vertex dEQP-GLES2.functional.shaders.operator.common_functions.sign.lowp_float_fragment dEQP-GLES2.functional.shaders.operator.common_functions.sign.mediump_float_vertex dEQP-GLES2.functional.shaders.operator.common_functions.sign.mediump_float_fragment dEQP-GLES2.functional.shaders.operator.common_functions.sign.highp_float_vertex dEQP-GLES2.functional.shaders.operator.common_functions.sign.highp_float_fragment dEQP-GLES2.functional.shaders.operator.common_functions.sign.lowp_vec3_vertex dEQP-GLES2.functional.shaders.operator.common_functions.sign.lowp_vec3_fragment dEQP-GLES2.functional.shaders.operator.common_functions.sign.mediump_vec3_vertex dEQP-GLES2.functional.shaders.operator.common_functions.sign.mediump_vec3_fragment dEQP-GLES2.functional.shaders.operator.common_functions.sign.highp_vec3_vertex dEQP-GLES2.functional.shaders.operator.common_functions.sign.highp_vec3_fragment Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* r600: Correct IDIV if DST and SRC use the same temporaryGert Wollny2018-05-281-3/+49
| | | | | | | | | | | | | | | | | In cases like IDIV TEMP[0].xy TEMP[0].xx TEMP[1].yy the result will be written to the same register that is also a source register. Since the components are evaluated one by one, this may result in overwriting the source value for a later operation. Work around this by adding another temporary to store the result if the destination temporary index is equal to one of the source temporary indices. Fixes: dEQP-GLES2.functional.shaders.operator.binary_operator.div.* Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radeonsi: remove unused variable addr_vecMarek Olšák2018-05-251-1/+1
| | | | trivial
* radeonsi: fix passing gl_ClipVertex for GS and tessMarek Olšák2018-05-253-4/+8
| | | | | | Also add the fprintf call. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: fix color inputs/outputs for GS and tessMarek Olšák2018-05-253-20/+34
| | | | | | | | | | GS is tested, tessellation is untested. Have outputs_written_before_ps for HW VS and outputs_written for other stages. The reason is that COLOR and BCOLOR alias for HW VS, which drives elimination of VS outputs based on PS inputs. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: fix incorrect parentheses around VS-PS varying eliminationMarek Olšák2018-05-251-2/+2
| | | | | | | I don't know if it caused issues. Cc: 18.0 18.1 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* swr/rast: Adjusted avx512 primitive assembly for msvc codegenAlok Hota2018-05-251-49/+90
| | | | | | | | | Optimize AVX-512 PA Assemble (PA_STATE_OPT). Reduced generated code by about 4x, MSVC compiler was going crazy making temporaries and split-loading inputs onto the stack unless explicit AVX-512 load ops were added Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Moved memory init out of core swr initAlok Hota2018-05-257-7/+86
| | | | | | | | Added two new files for a wrapper function for initialization v2: added missing include for single architecture builds Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Removed superfluous JitManager argument from passesAlok Hota2018-05-256-14/+13
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Renamed MetaData callsAlok Hota2018-05-252-87/+87
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
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