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* radeonsi: remove llvm_type_is_64bitMarek Olšák2020-01-153-17/+7
| | | | | Reviewed-by: Timothy Arceri <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3399>
* radeonsi: move tessellation shader code into si_shader_llvm_tess.cMarek Olšák2020-01-156-1290/+1343
| | | | | Reviewed-by: Timothy Arceri <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3399>
* radeonsi: move si_insert_input_* functionsMarek Olšák2020-01-152-28/+28
| | | | | Reviewed-by: Timothy Arceri <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3399>
* radeonsi: work around an LLVM crash when using llvm.amdgcn.icmp.i64.i1Marek Olšák2020-01-151-0/+1
| | | | | | | Cc: 19.2 19.3 <[email protected]> Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3338> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3338>
* radeonsi: fix si_build_wrapper_function for compute-based primitive cullingMarek Olšák2020-01-151-1/+14
| | | | | | | Fixes: 3b143369a55 "ac/nir, radv, radeonsi: Switch to using ac_shader_args" Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3338>
* radeonsi/gfx10: separate code for determining the number of vertices for NGGMarek Olšák2020-01-151-25/+41
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi/gfx10: separate code for getting edgeflags from the ↵Marek Olšák2020-01-151-9/+13
| | | | | | gs_invocation_id VGPR Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi: move VS_STATE.LS_OUT_PATCH_SIZE a few bits higher to make space thereMarek Olšák2020-01-153-5/+8
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi: make si_insert_input_* functions non-staticMarek Olšák2020-01-152-9/+12
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi: separate code computing info for small primitive cullingMarek Olšák2020-01-153-40/+54
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi: drop the negation from fmask_is_not_identityPierre-Eric Pelloux-Prayer2020-01-154-5/+5
| | | | | | | | | | | This change eases code reading ("fmask_is_identity = true" is clearer than "fmask_is_not_identity = false"). Initialization is not changed so fmask_is_identity is false when a texture is created. Reviewed-by: Marek Olšák <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3174> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3174>
* radeonsi: unbind image before compute clearPierre-Eric Pelloux-Prayer2020-01-151-0/+5
| | | | | | | It's not used and avoid infinite recursion when used from si_compute_expand_fmask Reviewed-by: Marek Olšák <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3174>
* radeonsi: make sure fmask expand is done if neededPierre-Eric Pelloux-Prayer2020-01-151-1/+2
| | | | | | | Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2248 Fixes: 095a58204d9 ("radeonsi: expand FMASK before MSAA image stores are used") Reviewed-by: Marek Olšák <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3174>
* radeonsi: fix fmask expand compute shaderPierre-Eric Pelloux-Prayer2020-01-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'coord' variable was using TGSI_WRITEMASK_XYZ so subsequent uses of TGSI_WRITEMASK_W were dropped. The result for a 2 samples program was: 0: UMAD TEMP[0].xy, SV[1].xyyy, IMM[0].xxxx, SV[0].xyyy 1: STORE IMAGE[0], TEMP[0], TEMP[1], RESTRICT, 2D_MSAA 2: STORE IMAGE[0], TEMP[0], TEMP[2], RESTRICT, 2D_MSAA 3: END instead of the expected: 0: UMAD TEMP[0].xy, SV[1].xyyy, IMM[0].xxxx, SV[0].xyyy 1: MOV TEMP[0].w, IMM[0].yyyy 2: LOAD TEMP[1], IMAGE[0], TEMP[0], RESTRICT, 2D_MSAA 3: MOV TEMP[0].w, IMM[0].zzzz 4: LOAD TEMP[2], IMAGE[0], TEMP[0], RESTRICT, 2D_MSAA 5: MOV TEMP[0].w, IMM[0].yyyy 6: STORE IMAGE[0], TEMP[0], TEMP[1], RESTRICT, 2D_MSAA 7: MOV TEMP[0].w, IMM[0].zzzz 8: STORE IMAGE[0], TEMP[0], TEMP[2], RESTRICT, 2D_MSAA 9: END This fixes half of https://gitlab.freedesktop.org/mesa/mesa/issues/2248 Fixes: 095a58204d9 ("radeonsi: expand FMASK before MSAA image stores are used") Reviewed-by: Marek Olšák <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3174>
* v3d: fix bug when checking result of syncobj fence importIago Toral Quiroga2020-01-151-1/+1
| | | | | | Reviewed-by: Alejandro Piñeiro <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3383> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3383>
* radeonsi: move PS LLVM code into si_shader_llvm_ps.cMarek Olšák2020-01-147-1283/+1317
| | | | | | | | This is an attempt to clean up si_shader.c. v2: don't move code that is not specific to LLVM Reviewed-by: Timothy Arceri <[email protected]> (v1)
* radeonsi: remove always constant ballot_mask_bits from si_llvm_context_initMarek Olšák2020-01-143-10/+6
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* radeonsi: fold si_create_function into si_llvm_create_funcMarek Olšák2020-01-144-43/+30
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* radeonsi: rename si_shader_create -> si_create_shader_variant for clarityMarek Olšák2020-01-144-8/+10
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* radeonsi: rename si_compile_tgsi_main -> si_build_main_functionMarek Olšák2020-01-141-5/+5
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* radeonsi: clean up si_shader_infoMarek Olšák2020-01-143-131/+45
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* radeonsi: merge si_tessctrl_info into si_shader_infoMarek Olšák2020-01-144-23/+10
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* radeonsi: fork tgsi_shader_info and tgsi_tessctrl_infoMarek Olšák2020-01-1412-56/+205
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* radeonsi: rename si_shader_info -> si_shader_binary_infoMarek Olšák2020-01-141-2/+2
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* radeonsi: remove TGSI from commentsMarek Olšák2020-01-144-11/+9
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* radeonsi: rename DBG_NO_TGSI -> DBG_NO_NIRMarek Olšák2020-01-143-3/+3
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* radeonsi: don't adjust depth and stencil PS output locationsMarek Olšák2020-01-142-11/+3
| | | | | | this was for compatibility with TGSI Reviewed-by: Timothy Arceri <[email protected]>
* panfrost: Fix linear depth texturesAlyssa Rosenzweig2020-01-144-20/+26
| | | | | | | | | | | | | | | | As pointed out by Boris, what we were calling PAN_LINEAR depth textures was in fact u-interleaved tiled (!), but we never noticed since we flipped the flag used for sampling, leading to all sorts of fun bugs when attempting to directly acess depth textures from the CPU. Which begs the question -- if what we called LINEAR was tiled, how do we actually render linear depth textures? It turns out the flags for AFBC form a mali_block_format 2-bit code just like their render-target counterparts, so we can render to any of the above. Signed-off-by: Alyssa Rosenzweig <[email protected]> Reported-by: Boris Brezillon <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3393> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3393>
* radeonsi: actually enable VBOs in user SGPRsMarek Olšák2020-01-141-1/+1
| | | | | Fixes: 363b4027fcb - radeonsi: put up to 5 VBO descriptors into user SGPRs Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi: fix assertion and other failures in si_emit_graphics_shader_pointersMarek Olšák2020-01-141-3/+4
| | | | | | | The assertion was failing. Fixes: 363b4027fcb - radeonsi: put up to 5 VBO descriptors into user SGPRs Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* etnaviv: Fix assert when try to accumulate an invalid fdMarco Felsch2020-01-141-1/+2
| | | | | | | | | | Check if it is a valid fd before merging it to the context's fd. Signed-off-by: Marco Felsch <[email protected]> Signed-off-by: Lucas Stach <[email protected]> Reviewed-by: Jonathan Marek <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3381> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3381>
* iris: Implement Gen12 workaround for non pipelined stateLionel Landwerlin2020-01-141-0/+39
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3365>
* lima: add new findings to texture descriptorVasily Khoruzhick2020-01-134-12/+47
| | | | | | | | | | | | | | | | | | | Lower 8 bits of unknown_1_3 seems to be min_lod, rest of 4 bits + miplevels are max_lod and min_mipfilter seems to be lod bias. All are in fixed format with 4 bit integer and 4 bit fraction, lod_bias also has sign bit. Blob also seems to do some magic with lod_bias if min filter is nearest -- it adds 0.5 to lod_bias in this case. Same story when all filters are nearest and mipmapping is enabled, but in this case it subtracts 1/16 from lod_bias. Fixes 134 dEQP tests in dEQP-GLES2.functional.texture.* Reviewed-by: Qiang Yu <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3359> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3359>
* iris: Simplify iris_get_renderer_string()Kenneth Graunke2020-01-131-11/+4
| | | | | | | | | We use gen_get_device_name() instead of PCI ID list munging. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3371>
* zink: fixup initialization of operand_mask / num_extra_operandsErik Faye-Lund2020-01-141-2/+2
| | | | | | This doesn't change behavior, but makes the code a bit easier to read. Both values are zero, but I somehow swapped the logical meaning of them when initializing.
* radeonsi: don't enable VBOs in user SGPRs if compute-based culling can be usedMarek Olšák2020-01-133-30/+46
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi: put up to 5 VBO descriptors into user SGPRsMarek Olšák2020-01-1310-62/+148
| | | | | | | | | | | | | | | | | | | | | gfx6-8: 1 VBO descriptor in user SGPRs gfx9-10: 5 VBO descriptors in user SGPRs We no longer pull up to 5 VBO descriptors from GTT when SDMA is disabled. Totals from affected shaders: SGPRS: 1110528 -> 1170528 (5.40 %) VGPRS: 952896 -> 951936 (-0.10 %) Spilled SGPRs: 83 -> 61 (-26.51 %) Spilled VGPRs: 0 -> 0 (0.00 %) Private memory VGPRs: 0 -> 0 (0.00 %) Scratch size: 0 -> 0 (0.00 %) dwords per thread Code Size: 23766296 -> 22843920 (-3.88 %) bytes LDS: 0 -> 0 (0.00 %) blocks Max Waves: 179344 -> 179344 (0.00 %) Wait states: 0 -> 0 (0.00 %) Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* ac,radeonsi: increase the maximum number of shader args and return valuesMarek Olšák2020-01-131-6/+6
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi: simplify si_set_vertex_buffersMarek Olšák2020-01-131-7/+8
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi: don't allow draw calls with uninitialized VS inputsMarek Olšák2020-01-133-1/+8
| | | | | | These always hang, because vertex buffer descriptors are not set up. Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi: add si_context::num_vertex_elementsMarek Olšák2020-01-133-11/+7
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi: rename desc_list_byte_size -> vb_desc_list_alloc_sizeMarek Olšák2020-01-135-11/+9
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* nir/lower_atomics_to_ssbo: Also lower barriersJason Ekstrand2020-01-131-2/+0
| | | | | | | | | | | This is more correct for a pass which is supposed to completely lower away atomic counters. It also lets us stop supporting atomic counter barriers in most of the drivers. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3307> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3307>
* nir: Rename nir_intrinsic_barrier to control_barrierJason Ekstrand2020-01-131-1/+1
| | | | | | | | This is a more explicit name now that we don't want it to be doing any memory barrier stuff for us. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3307>
* nir: Add a new memory_barrier_tcs_patch intrinsicJason Ekstrand2020-01-131-0/+2
| | | | | | | | | | | Right now, it's implemented as a no-op for everyone. For most drivers, it's a switch case in the NIR -> whatever which just breaks. For ir3, they already have code to delete tessellation barriers so we just add a case to also delete memory_barrier_tcs_patch. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3307>
* lima: Add stencil supportAndreas Baierl2020-01-132-27/+64
| | | | | | | | | | | | | | This re-enables and fixes support for stencil buffer. It fixes 365 stencil related deqp tests. All tests that use INCR, INCR_WRAR, DECR and DECR_WRAP as a stencil op still fail, but they also fail with the blob, so we may ignore that for now. We still have dEQP-GLES2.functional.depth_stencil_clear.depth_stencil_masked failing, which is strange because it's the only one out of the depth_stencil_clear.* set. Reviewed-by: Vasily Khoruzhick <[email protected]> Signed-off-by: Andreas Baierl <[email protected]>
* lima/parser: Make rsw alpha blend parsing more readableAndreas Baierl2020-01-131-4/+5
| | | | | Reviewed-by: Vasily Khoruzhick <[email protected]> Signed-off-by: Andreas Baierl <[email protected]>
* panfrost: Fix headers and gpu_headers memory leakDaniel Ogorchock2020-01-131-0/+3
| | | | | | | | | | The per-batch headers/gpu_headers dynarrays need to be freed during the batch cleanup to prevent leaking. Signed-off-by: Daniel Ogorchock <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3308> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3308>
* panfrost: Fix panfrost_bo_access memory leakDaniel Ogorchock2020-01-131-1/+3
| | | | | | | | | The bo access needs to be freed prior to removing it from its hash table. This prevents leaking them over time. Signed-off-by: Daniel Ogorchock <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3308>
* nvc0: treat all draws without color0 broadcast as MRTIlia Mirkin2020-01-121-1/+1
| | | | | | | | | | | Per the semi-recently-released NVIDIA docs, when this bit is not enabled, then the result for RT[0] will be used. So if e.g. only a single RT is drawn to and it's not RT[2], the results will not be visible. Fixes GTF-GL45.gtf33.GL3Tests.explicit_attrib_location.explicit_attrib_location_pipeline which was failing due to a frag shader outputting only to location=2. Signed-off-by: Ilia Mirkin <[email protected]>
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