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* broadcom/vc4: Don't advertise tiled dmabuf modifiers if we can't use themDerek Foreman2017-10-051-13/+18
| | | | | | | | | | | | | | | | If the DRM_VC4_GET_TILING ioctl isn't present then we can't tell if a dmabuf bo is tiled or linear, so will always assume it's linear. By not advertising tiled formats in this situation we ensure the assumption is correct. This fixes a bug where most attempts to render a gl wayland client under weston will result in a client side abort. Signed-off-by: Derek Foreman <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Acked-by: Daniel Stone <[email protected]> (on irc)
* llvmpipe: silence 'variable may be used uninitialized' warningsBrian Paul2017-10-031-1/+1
| | | | Reviewed-by: Charmaine Lee <[email protected]>
* svga: wrap long comments in svga_tgsi_vgpu10.cBrian Paul2017-10-031-4/+6
| | | | Trivial.
* svga: tweak pre-VGPU10 rasterization offsetsBrian Paul2017-10-031-17/+7
| | | | | | | | | | | | | | | | | | | | It seems there's no perfect x/y biases for line drawing to satisfy all applications. Depending on the biases, either real apps produce results similar to VGPU10 while Piglit's gl-1.0-ortho-pos fails, or vice versa. Let's lean toward real applications (Solidworks, SolidEdge, Google Earth) over Piglit. Using (-0.5, -0.5) for points, lines and triangles, seems to generally work well. We don't seem to have these issues with VGPU10. Tested with Piglit and CAD-oriented apitraces. See VMware bugs 1775498 and 1905053. Reviewed-by: José Fonseca <[email protected]> Reviewed-by: Charmaine Lee <[email protected]>
* svga: if we get nr_samples==1, store nr_samples=0Brian Paul2017-10-031-4/+7
| | | | | | | | | | We need to be more careful not to treat nr_samples=1 as an msaa surface. This patch prevents us from errantly declaring an MSAA shader resource with 1 sample. No Piglit regressions, fixes the above-described errors. Reviewed-by: Neha Bhende <[email protected]>
* svga: emit sampler constants only if sampler view existsCharmaine Lee2017-10-031-7/+12
| | | | | | | | | | | | | | It is possible to have holes in the shader emitter's sampler_target array. 0 sampler_target does not necessarily mean there is no sampler view specified since texture buffer target has the value 0. With this patch, a sampler_view array is added to the shader emitter structure to specify if there is a sampler view for each texture unit. Only if there is a sampler view, we will emit constant for texcoord scale factor or texture buffer size for that sampler view. Fixes a rendering issue with Turbine after commit 1020e960440. Reviewed-by: Brian Paul <[email protected]>
* svga: fix incorrect case in svga_typeless_format()Brian Paul2017-10-031-2/+1
| | | | | | | | | | | | For the case of SVGA3D_X32_G8X24_UINT we incorrectly returned SVGA3D_R32_FLOAT_X8X24. We should return SVGA3D_R32G8X24_TYPELESS. Note that we never actually use SVGA3D_X32_G8X24_UINT so this has no impact. No Piglit regressions. Reviewed-by: Charmaine Lee <[email protected]>
* svga: add typeless switch cases in svga_typeless_format()Brian Paul2017-10-031-0/+10
| | | | | | | | | | We sometimes pass typeless formats to this function. By adding switch cases we avoid the "Unexpected format XXX in svga_typeless_format" warning messages. No functional change. No Piglit regressions, no above-mentioned warning messages. Reviewed-by: Charmaine Lee <[email protected]>
* svga: Allow sRGB format with PIPE_BIND_DISPLAY_TARGET binding flag on vgpu10.Neha Bhende2017-10-031-2/+7
| | | | | | | This patch allows to use sRGB formats for DISPLAY_TARGET on vgpu10. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Charmaine Lee <[email protected]>
* etnaviv: Set up unknown GC3000 statesWladimir J. van der Laan2017-10-031-0/+11
| | | | | | | | | | | Set up new states that the blob started setting for GC3000 consistently. This makes sure that when another test or driver leaves the GPU in unpredictable state, these states are set up correctly for our rendering. Signed-off-by: Wladimir J. van der Laan <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: Fix point sprite rendering on GC3000Wladimir J. van der Laan2017-10-031-0/+2
| | | | | | | | Setting PA_VIEWPORT_UNK state correctly is necessary to make point sprite rendering on GC3000 work. Signed-off-by: Wladimir J. van der Laan <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: Add support for DP2 instructionWladimir J. van der Laan2017-10-034-1/+7
| | | | | | | | A two-component dot product instruction is supported with HALTI2, use it on hardware that supports it. Signed-off-by: Wladimir J. van der Laan <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: Support opcodes with bit 6 set in assemblerWladimir J. van der Laan2017-10-031-1/+4
| | | | | | | | Support opcodes with bit 6 set in assembler, and assert that only ops 0x00..0x7f are used. Signed-off-by: Wladimir J. van der Laan <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* gallium: Remove util_format_s3tc_init()Matt Turner2017-10-0211-18/+0
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* gallium: Remove util_format_s3tc_enabledMatt Turner2017-10-029-33/+2
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* freedreno/a5xx: fix missing restore stateRob Clark2017-10-021-0/+3
| | | | | | | | RB_CLEAR_CNTL seems to be in a funny state after boot (at least on 8x96/a530). Cc: 17.2 <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* swr/rast: do not crash on NULL strings returned by getenvEmil Velikov2017-10-021-1/+2
| | | | | | | | | | | | | | | | | | | | The current convenience function GetEnv feeds the results of getenv directly into std::string(). That is a bad idea, since the variable may be unset, thus we feed NULL into the C++ construct. The latter of which is not allowed and leads to a crash. v2: Better variable name, implicit char* -> std::string conversion (Eric) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101832 Fixes: a25093de718 ("swr/rast: Implement JIT shader caching to disk") Cc: Tim Rowley <[email protected]> Cc: Laurent Carlier <[email protected]> Cc: Bernhard Rosenkraenzer <[email protected]> [Emil Velikov: make an actual commit from the misc diff] Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> (v1) Reviewed-by: Laurent Carlier <[email protected]> (v1)
* freedreno/a5xx: align height to GMEMRob Clark2017-10-021-1/+5
| | | | | | | | | | | | | | | | | Similar to the way width/pitch alignment works, it seems like we need to do similar for height. Otherwise the BLIT from system memory to GMEM can over-fetch beyond the end of the buffer, triggering a fault. I'm not sure if there is a better solution yet. Possibly we could fall back to pre-a5xx style DRAW packets for cases where BLIT might over- fetch. (We in theory have that problem already with rendering to higher mipmap levels, although fortunately those tend to use GMEM bypass.) This fixes issues reported with glamor. Reported-by: [email protected] Cc: 17.2 <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* radeonsi: adjust clip discard based on line width / point sizeNicolai Hähnle2017-10-023-11/+27
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: remove si_context::{scissor_enabled,clip_halfz}Nicolai Hähnle2017-10-023-26/+24
| | | | | | They are just copies of the rasterizer state. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: simplify the signature of si_update_vs_writes_viewport_indexNicolai Hähnle2017-10-023-7/+6
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: move current_rast_prim into si_contextNicolai Hähnle2017-10-026-15/+11
| | | | | | v2: rebase fixes Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: move and rename scissor and viewport state and functionsNicolai Hähnle2017-10-0210-182/+184
| | | | | | v2: change GET_MAX_SCISSOR to SI_MAX_SCISSOR Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: remove si_apply_scissor_bug_workaroundNicolai Hähnle2017-10-022-19/+0
| | | | | | It only affects pre-SI chips. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: move r600_viewport.c to si_viewport.cNicolai Hähnle2017-10-023-2/+2
| | | | | | | This is purely a file-move + #include fixup + build system changes. Other cleanups will follow in subsequent commits. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: fix maximum advertised point size / line widthNicolai Hähnle2017-10-022-8/+3
| | | | | | | | | | The hardware registers store the half-size/width in 12.4 fixed point format, so 8192 is the maximum. Fixes dEQP-GLES3.functional.rasterization.* Cc: [email protected] Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: deduce rast_prim correctly for tessellation point modeNicolai Hähnle2017-10-021-3/+6
| | | | | | | | Together with the previous patches, this fixes dEQP-GLES31.functional.primitive_bounding_box.wide_points.* Cc: [email protected] Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: don't discard points and linesNicolai Hähnle2017-10-022-2/+26
| | | | | | | | | This is a bit conservative, but a more precise solution requires access to the rasterizer state. This is something to tackle after the fork between r600 and radeonsi. Cc: [email protected] Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: move current_rast_prim to r600_common_contextNicolai Hähnle2017-10-025-9/+13
| | | | | | | | | | We'll use it in the scissors / clip / guardband state. v2: avoid a performance regression on r600 when applied to (pre-fork) stable branches Cc: [email protected] Reviewed-by: Marek Olšák <[email protected]>
* gallium: add PIPE_FORMAT_R10G10B10X2_UNORMNicolai Hähnle2017-10-021-0/+1
| | | | Reviewed-by: Marek Olšák <[email protected]>
* freedreno: fix PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVERob Clark2017-10-022-4/+5
| | | | | | | | Fixes an assert in fd_acc_query_register_provider() about query provider not already registered. Fixes: 3f6b3d9d ("gallium: add PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE") Signed-off-by: Rob Clark <[email protected]>
* radeonsi: fix a regression in integer cube map handlingNicolai Hähnle2017-10-021-8/+26
| | | | | | | | | | | | A recent commit fixed the case of 8888 integer cube maps, which need the workaround of replacing the data format with USCALED/SSCALED. However, this broke the case of non-8888 integer cube maps; those still need the fix of shifting the texture coordinates. Fixes KHR-GL45.texture_gather.plain-gather-int-cube-array and similar. Fixes: 6fb0c1013b35 ("radeonsi: workaround for gather4 on integer cube maps") Reviewed-by: Marek Olšák <[email protected]>
* amd/common: move ac_build_phi from radeonsiNicolai Hähnle2017-10-021-17/+3
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: don't use the template keywordMarek Olšák2017-09-301-7/+7
| | | | | | for C++ editors Reviewed-by: Brian Paul <[email protected]>
* radeonsi/uvd: clean up si_video_buffer_createBenedikt Schemmer2017-09-301-30/+17
| | | | | | V2: remove code duplication and one unnessecary variable, minor whitespace fix Signed-off-by: Marek Olšák <[email protected]>
* radeonsi/uvd: fix planar formats broken since f70f6baaa3bb0f8b280ac2eaea69bbMarek Olšák2017-09-301-3/+8
| | | | | Tested-by: Benedikt Schemmer <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeonsi: emit DLDEXP and DFRACEXP TGSI opcodesNicolai Hähnle2017-09-292-1/+26
| | | | | | | | | Note: this causes spurious regressions in some current piglit tests, because the tests incorrectly assume that there is no denorm support for doubles. I'm going to send out a fix for those tests as well. Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* radeonsi: emit LDEXP opcodeNicolai Hähnle2017-09-292-1/+3
| | | | | | | | The LLVM intrinsic has existed for a long time. The current name was established in LLVM 3.9. Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* gallium: add LDEXP TGSI instruction and corresponding capNicolai Hähnle2017-09-2911-0/+15
| | | | | Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* tgsi: infer that dst[1] of DFRACEXP is an integerNicolai Hähnle2017-09-291-1/+1
| | | | | Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* gallivm: add dst register index to lp_build_tgsi_context::emit_storeNicolai Hähnle2017-09-293-11/+18
| | | | | Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* tgsi: clarify the semantics of DFRACEXPNicolai Hähnle2017-09-291-6/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The status quo is quite the mess: 1. tgsi_exec will do a per-channel computation, and store the dst[0] result (significand) correctly for each channel. The dst[1] result (exponent) will be written to the first bit set in the writemask. So per-component calculation only works partially. 2. r600 will only do a single computation. It will replicate the exponent but not the significand. 3. The docs pretend that there's per-component calculation, but even get dst[0] and dst[1] confused. 4. Luckily, st_glsl_to_tgsi only ever emits single-component instructions, and kind-of assumes that everything is replicated, generating this for the dvec4 case: DFRACEXP TEMP[0].xy, TEMP[1].x, CONST[0][0].xyxy DFRACEXP TEMP[0].zw, TEMP[1].y, CONST[0][0].zwzw DFRACEXP TEMP[2].xy, TEMP[1].z, CONST[0][1].xyxy DFRACEXP TEMP[2].zw, TEMP[1].w, CONST[0][1].zwzw Settle on the simplest behavior, which is single-component calculation with replication, document it, and adjust tgsi_exec and r600. Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* r600: cleanup set_occlusion_query_stateNicolai Hähnle2017-09-293-14/+3
| | | | | | | | | | | This fixes a warning caused by the fork (note the change in the function signature): ../../../../../mesa-src/src/gallium/drivers/r600/r600_state_common.c: In function ‘r600_init_common_state_functions’: ../../../../../mesa-src/src/gallium/drivers/r600/r600_state_common.c:2974:36: warning: assignment from incompatible pointer type [-Wincompatible-pointer-types] rctx->b.set_occlusion_query_state = r600_set_occlusion_query_state; Reviewed-by: Marek Olšák <[email protected]>
* r300: add missing case PIPE_SHADER_CAP_INT64_ATOMICSNicolai Hähnle2017-09-291-0/+1
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: fix border color translation for integer texturesNicolai Hähnle2017-09-293-29/+60
| | | | | | | | | | This fixes the extremely unlikely case that an application uses 0x80000000 or 0x3f800000 as border color for an integer texture and helps in the also, but perhaps slightly less, unlikely case that 1 is used as a border color. Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* radeonsi: clamp border colors for upgraded depth texturesNicolai Hähnle2017-09-291-59/+60
| | | | | | | | | | | | | The hardware does this automatically for unorm formats, but we need to do it manually for unorm depth formats that have been upgraded to Z32_FLOAT. Fixes dEQP-GLES31.functional.texture.border_clamp.range_clamp.nearest_unorm_depth and others. Fixes: d4d9ec55c589 ("radeonsi: implement TC-compatible HTILE") Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* radeonsi: clamp depth comparison value only for fixed point formatsNicolai Hähnle2017-09-296-14/+53
| | | | | | | | | | | | | | | | | | | The hardware usually does this automatically. However, we upgrade depth to Z32_FLOAT to enable TC-compatible HTILE, which means the hardware no longer clamps the comparison value for us. The only way to tell in the shader whether a clamp is required seems to be to communicate an additional bit in the descriptor table. While VI has some unused bits in the resource descriptor, those bits have unfortunately all been used in gfx9. So we use an unused bit in the sampler state instead. Fixes dEQP-GLES3.functional.texture.shadow.2d.linear.equal_depth_component32f and many other tests in dEQP-GLES3.functional.texture.shadow.* Fixes: d4d9ec55c589 ("radeonsi: implement TC-compatible HTILE") Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* radeonsi/gfx9: fix geometry shaders without output verticesNicolai Hähnle2017-09-291-3/+5
| | | | | | | | | | | Not that those are super common or useful, but hey! Fun corner cases of the API... Fixes dEQP-GLES31.functional.geometry_shading.emit.* Cc: [email protected] Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* radeonsi: move descriptor logs to after corresponding draw/compute packetNicolai Hähnle2017-09-292-8/+6
| | | | | | | | It has to happen after descriptor uploads since otherwise we'll print out the wrong GPU list / incorrectly claim descriptor corruption. Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* amd/common: remove ac_shader_abi::chip_classNicolai Hähnle2017-09-291-2/+0
| | | | | | | Redundant with the recently added ac_llvm_context::chip_class. Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
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