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* radeonsi: capitalize VM hex addr when dumping buffer listSamuel Pitoiset2017-01-041-1/+1
* r600/sb: Fix loop optimization related hangs on egHeiko Przybyl2017-01-036-30/+68
* freedreno/ir3: rework varying slots (maybe??)Rob Clark2016-12-301-4/+9
* nir: Rename convert_to_ssa lower_regs_to_ssaJason Ekstrand2016-12-292-2/+2
* vc4: Rework scheduling of thread switch to cut one more NOP.Eric Anholt2016-12-291-46/+75
* vc4: Fill thread switching delay slotsJonas Pfeil2016-12-291-7/+38
* vc4: Enable NIR-based loop unrolling.Eric Anholt2016-12-291-0/+5
* freedreno/ir3: fix linkage::var sizeRob Clark2016-12-271-1/+1
* freedreno/ir3: treat clipvertex like a normal varyingRob Clark2016-12-271-3/+1
* freedreno/a5xx: transform-feedback supportRob Clark2016-12-277-38/+209
* freedreno: update generated headersRob Clark2016-12-277-43/+81
* freedreno/ir3: UBO support for 64b GPUs (a5xx)Rob Clark2016-12-271-3/+24
* freedreno/ir3: rework location of driver constantsRob Clark2016-12-276-53/+75
* freedreno/a5xx: fix emit for bo addressesRob Clark2016-12-271-3/+9
* freedreno/a5xx: texture layoutRob Clark2016-12-272-2/+2
* swr: fix icc compile errorBruce Cherniak2016-12-231-1/+1
* radeonsi: Bugfix needed for hashcatChristian Inci2016-12-221-5/+7
* radeonsi: fix gl_ClipDistance and gl_ClipVertex for pointsNicolai Hähnle2016-12-221-2/+10
* radeonsi: only set VS_OUT_MISC_SIDE_BUS_ENA when the misc vector is usedNicolai Hähnle2016-12-221-5/+6
* llvmpipe: Link tests with CLOCK_LIB.Vinson Lee2016-12-211-1/+2
* radeonsi: add Polaris12 support (v3)Junwei Zhang2016-12-214-1/+7
* svga: Fix a strict-aliasing violation in shader dumperEdward O'Callaghan2016-12-211-1/+9
* freedreno/a5xx: border color supportRob Clark2016-12-181-3/+160
* freedreno/a5xx: use MRT0 to import linear zsRob Clark2016-12-181-5/+20
* freedreno: fdN_gmem_restore_format() is not gen specificRob Clark2016-12-188-50/+25
* freedreno/a5xx: cargo-cult end-batch sequence more faithfullyRob Clark2016-12-184-4/+39
* freedreno/a5xx: misc fixRob Clark2016-12-181-1/+1
* freedreno/a5xx: fix (at least some) vtx formatsRob Clark2016-12-181-1/+1
* freedreno/a5xx: more formatsRob Clark2016-12-181-25/+25
* freedreno/a5xx: fixup capsRob Clark2016-12-182-6/+11
* freedreno/a5xx: fix random faults on first sysmem drawRob Clark2016-12-181-0/+3
* freedreno: update generated headersRob Clark2016-12-186-17/+80
* freedreno/a5xx: fix stride/size for mem->gmem blitsRob Clark2016-12-181-5/+7
* swr: Implement fence attached work queues for deferred deletion.Bruce Cherniak2016-12-169-54/+255
* treewide: s/comparitor/comparator/Ilia Mirkin2016-12-122-2/+2
* swr: [rasterizer core/memory] StoreTile: AVX512 progressTim Rowley2016-12-122-222/+138
* radeonsi: shrink the GSVS ring to account for the reduced item sizesNicolai Hähnle2016-12-121-1/+1
* radeonsi: shrink each vertex stream to the actually required sizeNicolai Hähnle2016-12-122-25/+40
* radeonsi: use a single descriptor for the GSVS ringNicolai Hähnle2016-12-124-50/+67
* radeonsi: pack GS output components for each vertex stream contiguouslyNicolai Hähnle2016-12-121-3/+8
* radeonsi: do not write non-existent components through the GSVS ringNicolai Hähnle2016-12-121-2/+4
* radeonsi: only write values belonging to the stream when emitting GS vertexNicolai Hähnle2016-12-121-0/+3
* radeonsi: generate an explicit switch instruction over vertex streamsNicolai Hähnle2016-12-121-8/+13
* radeonsi: fetch only outputs of current vertex stream from the GSVS ringNicolai Hähnle2016-12-121-16/+25
* radeonsi: only export from GS copy shader for vertex stream 0Nicolai Hähnle2016-12-121-12/+19
* radeonsi: do not export VS outputs from vertex streams != 0Nicolai Hähnle2016-12-121-0/+6
* radeonsi: pull iteration over vertex streams into GS copy shader logicNicolai Hähnle2016-12-121-25/+37
* radeonsi: group streamout writes by vertex streamNicolai Hähnle2016-12-121-10/+22
* radeonsi: load the streamout buf descriptors closer to their useNicolai Hähnle2016-12-121-14/+11
* radeonsi: extract writing of a single streamout outputNicolai Hähnle2016-12-121-39/+52
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