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* nv50/ir: reduce degree limit on ops that can't encode large reg destsIlia Mirkin2015-12-081-3/+34
| | | | | | | Operations that take immediates can only encode registers up to 64. This fixes a shader in a "Powered by Unity" intro. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: only unspill once ahead of a group of instructionsIlia Mirkin2015-12-081-5/+20
| | | | | | | | | | | | | | | | | | | | | | | We already semi-did this but the list of uses as unsorted, so it was unreliable. Sort the uses by bb and serial, and don't unspill for each instruction in a sequence. (And also don't unspill multiple times for a single instruction that uses the value in question multiple times.) This causes a minor reduction in generated instructions for shader-db (as few programs spill) but more importantly it brings determinism to each run's output. On SM10: total instructions in shared programs : 6387945 -> 6379359 (-0.13%) total gprs used in shared programs : 728544 -> 728544 (0.00%) total local used in shared programs : 9904 -> 9904 (0.00%) local gpr inst bytes helped 0 0 322 322 hurt 0 0 0 0 Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: check if the target supports the new offset before inliningIlia Mirkin2015-12-084-3/+25
| | | | | | Fixes: abd326e81b (nv50/ir: propagate indirect loads into instructions) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93300 Signed-off-by: Ilia Mirkin <[email protected]>
* vc4: Enable MSAA.Eric Anholt2015-12-081-2/+3
| | | | | | | | We still have several failures in the newly enabled tests in simulation: sRGB downsampling is done as if it was just linear, stencil blits are not supported on MSAA either, and derivatives are still not supported (breaking some MSAA simulation shaders). So, other than sRGB downsampling quality, things seem to be in good shape.
* vc4: Add support for mapping of MSAA resources.Eric Anholt2015-12-082-8/+105
| | | | | The pipe_transfer_map API requires that we do an implicit downsample/upsample and return a mapping of that.
* vc4: Add support for texel fetches from MSAA resources.Eric Anholt2015-12-085-15/+295
| | | | | | | | This is the core of ARB_texture_multisample. Most of the piglit tests for GL_ARB_texture_multisample require GL 3.0, but exposing support for this lets us use the gallium blitter for multisample resolves. We can sometimes multisample resolve using just the RCL, but that requires that the blit is 1:1, unflipped, and aligned to tile boundaries.
* vc4: Add support for multisample framebuffer operations.Eric Anholt2015-12-087-24/+191
| | | | | | | | This includes GL_SAMPLE_COVERAGE, GL_SAMPLE_ALPHA_TO_ONE, and GL_SAMPLE_ALPHA_TO_COVAGE. I haven't implemented a dithering function yet, and gallium doesn't give me a good chance to do so for GL_SAMPLE_COVERAGE.
* vc4: Add a workaround for HW-2905, and additional failure I saw with MSAA.Eric Anholt2015-12-081-2/+16
| | | | | | I only stumbled on this while experimenting due to reading about HW-2905. I don't know if the EZ disable in the Z-clear is actually necessary, but go with it for now.
* vc4: Add support for drawing in MSAA.Eric Anholt2015-12-086-50/+148
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* vc4: Add kernel RCL support for MSAA rendering.Eric Anholt2015-12-085-39/+239
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* vc4: Rename color_ms_write to color_write.Eric Anholt2015-12-083-22/+21
| | | | | I was thinking this was the only MSAA resolve thing, so it should be noted separately, but actually load/store general also do MSAA resolve.
* vc4: Allow RCL blits to the edge of the surface.Eric Anholt2015-12-081-2/+8
| | | | | | | The recent unaligned fix successfully prevented RCL blits that weren't aligned inside of the surface, but we also want to be able to do RCL blits for the whole surface when the width or height of the surface aren't aligned (we don't care what renders inside of the padding).
* vc4: Add disabled debug printf for describing blits.Eric Anholt2015-12-081-0/+10
| | | | I keep typing variants of this while debugging RCL blits for MSAA.
* vc4: Fix check for tile RCL blits with mismatched y.Eric Anholt2015-12-081-1/+1
| | | | | This was a typo in 3a508a0d94d020d9cd95f8882e9393d83ffac377 that didn't show up in testcases at that moment.
* vc4: Fix compiler warning from size_t change.Eric Anholt2015-12-081-1/+1
| | | | I missed this when bringing over the kernel changes.
* radeonsi: last_gfx_fence is a winsys fenceNicolai Hähnle2015-12-071-1/+1
| | | | | Cc: "11.1" <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* nvc0/ir: fix up mul+add -> mad algebraic opt, enable for integersIlia Mirkin2015-12-073-12/+11
| | | | | | | For some reason this has been disabled for integers ever since codegen was merged, despite there being emission code for IMAD. Seems to work. Signed-off-by: Ilia Mirkin <[email protected]>
* gk110/ir: fix imad sat/hi flag emission for immediate argsIlia Mirkin2015-12-071-8/+3
| | | | | | | | According to nvdisasm both the immediate and non-imm cases use the same bits. Both of these flags are quite rarely set though. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.0 11.1" <[email protected]>
* gk104/ir: sampler doesn't matter for txfIlia Mirkin2015-12-071-1/+1
| | | | | | | | | | We actually leave the sampler unset for OP_TXF, which caused the GK104+ logic to treat some texel fetches as indirect. While this works, it's incredibly wasteful. This only happened when the texture was > 0 (since sampler remained == 0). Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.0 11.1" <[email protected]>
* radeonsi: disable DCC on StoneyMarek Olšák2015-12-071-0/+4
| | | | | Cc: 11.1 <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* gk110/ir: fix imul hi emission with limm argIlia Mirkin2015-12-071-2/+2
| | | | | | | The elemental demo hits this case. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.0 11.1" <[email protected]>
* svga: use the debug callback to report issues to the state trackerBrian Paul2015-12-076-0/+62
| | | | | | | | | | | | | | | Use the new debug callback hook to report conformance, performance and fallbacks to the state tracker. The state tracker, in turn can report this issues to the user via the GL_ARB_debug_output extension. More issues can be reported in the future; this is just a start. v2: remove conditionals around pipe_debug_message() calls since the check is now done in the macro itself. v3: remove unneeded dummy %s substitutions Acked-by: Ilia Mirkin <[email protected]>, Reviewed-by: José Fonseca <[email protected]>
* r600: apply SIMD workaround to cayman also.Dave Airlie2015-12-071-1/+8
| | | | | | | | | | | At last on ARUBA this is required to stop tessellation hanging in heaven. This removes one of the SIMDs from use by the HS/LS. Reviewed-by: Edward O'Callaghan <[email protected]> Tested-by: Edward O'Callaghan <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: fix regression introduced with ring emit changes.Dave Airlie2015-12-071-1/+2
| | | | This was adding one after a CUT which broke end primitive
* r600: remove stale tessellation commentDave Airlie2015-12-071-1/+0
| | | | | | pointed out by Marek. Signed-off-by: Dave Airlie <[email protected]>
* r600: enable tessellation for evergreen/cayman (v2)Dave Airlie2015-12-071-1/+9
| | | | | | | | | | This enables tessellation for evergreen/cayman, This will need changes before committing depending on what hw works etc. working are CAYMAN/REDWOOD/BARTS/TURKS/SUMO/CAICOS v2: only enable on evergreen and above.
* r600g: reduce number of ps thread on caicosDave Airlie2015-12-071-1/+1
| | | | | | this allows tess apps to start Signed-off-by: Dave Airlie <[email protected]>
* r600g: adjust ls/hs thread counts for sumoDave Airlie2015-12-071-4/+4
| | | | | | these stop tess hangs here. Signed-off-by: Dave Airlie <[email protected]>
* r600/asm: enable nstack check for tess ctrl/eval shaders.Dave Airlie2015-12-071-1/+1
| | | | | | | This just makes sure they register at least one stack usage frame like vertex shaders. Signed-off-by: Dave Airlie <[email protected]>
* r600/asm: handle lds read operations.Dave Airlie2015-12-071-1/+21
| | | | | | | | | Reads from the queue shouldn't be merged for now read operations. Reads from the queue shouldn't be merged for now, or put in T slots. Signed-off-by: Dave Airlie <[email protected]>
* r600/asm: add LDS ops and barrier to the once per group restriction.Dave Airlie2015-12-071-1/+1
| | | | | | | LDS ops must be scheduled in X slot, and barrier should be on its own in a group. Signed-off-by: Dave Airlie <[email protected]>
* r600: move VGT_VTX_CNT_EN into shader stages atom.Dave Airlie2015-12-071-2/+2
| | | | | | This should be enabled for tessellation shaders as well. Signed-off-by: Dave Airlie <[email protected]>
* r600: enable tcs/tes dumping for R600_DUMP_SHADERS.Dave Airlie2015-12-071-1/+1
| | | | | | Trivial patch just to enable dumping more. Signed-off-by: Dave Airlie <[email protected]>
* r600: handle SIMD allocation issue with HS/LSDave Airlie2015-12-071-0/+5
| | | | | | | | | At least one SIMD must be kept away from the HS/LS stages in order to avoid a hw issue on evergreen/cayman. This patch implements this workaround. Signed-off-by: Dave Airlie <[email protected]>
* r600/shader: increase number of inputs/outputs to 64.Dave Airlie2015-12-071-2/+2
| | | | | | Tessellation exceeds these sometimes, so increase them for now. Signed-off-by: Dave Airlie <[email protected]>
* r600: handle barrier opcode.Edward O'Callaghan2015-12-071-2/+17
| | | | | | | This handles the barrier opcode for EG/CM. Signed-off-by: Edward O'Callaghan <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600/shader: handle tess related system-values.Dave Airlie2015-12-071-2/+148
| | | | | | | | | | This adds handling for TESSINNER/TESSOUTER in the TES where they need to be fetched from LDS, and TESSCOORD which comes in via r0. It also handle primitive ID and invocation ID. Signed-off-by: Dave Airlie <[email protected]>
* r600/shader: allow multi-dimension arrays for tcs/tes inputs/outputs.Dave Airlie2015-12-071-2/+10
| | | | | | This just allows multi-dim arrays to be processed. Signed-off-by: Dave Airlie <[email protected]>
* r600/shader: handle TES exports and streamoutDave Airlie2015-12-071-7/+16
| | | | | | | | | | when tessellation is enabled the TES shader is responsible for handling streamout and exports. This adds the streamout and export workarounds to TES, and also makes sure TES sets up spi_sid. Signed-off-by: Dave Airlie <[email protected]>
* r600/shader: emit tessellation factors to GDS at end of TCS.Dave Airlie2015-12-071-1/+166
| | | | | | | | | | When we are finished the shader, we read back all the tess factors from LDS and write them to special global memory storage using GDS instructions. This also handles adding NOP when GDS or ENDLOOP end the TCS. Signed-off-by: Dave Airlie <[email protected]>
* r600/shader: handle TCS output writing.Dave Airlie2015-12-071-2/+98
| | | | | | | | | | TCS outputs whenever they are written in the shader, need to be written to LDS not temporaries, this handles this case. It also fixes up the case where the output is a relative addressed output, so we don't try to apply the relative address at the wrong time. Signed-off-by: Dave Airlie <[email protected]>
* r600/shader: handle VS shader writing to the LDS outputs. (v1.1)Dave Airlie2015-12-071-1/+75
| | | | | | | | This writes the VS shaders outputs to the LDS memory in the correct places. v1.1: use 24-bit Signed-off-by: Dave Airlie <[email protected]>
* r600/shader: handle fetching tcs/tes inputs and tcs outputsDave Airlie2015-12-071-1/+279
| | | | | | | | | | This handles the logic for doing fetches from LDS for TCS and TES. For TCS we need to fetch both inputs and outputs, for TES only inputs need to be fetched. v2: use 24-bit ops. Signed-off-by: Dave Airlie <[email protected]>
* r600/shader: add get_lds_offset0 helperDave Airlie2015-12-071-0/+22
| | | | | | | | This retrievs the offset into the LDS for a patch or non-patch variable, it takes the RelPatch channel and a temporary register. Signed-off-by: Dave Airlie <[email protected]>
* r600/shader: add function to get tess constants infoDave Airlie2015-12-071-1/+90
| | | | | | | | | This function retrieves the tess input/output info from the tess constant buffer that is bound to the shader. This uses a vfetch to get the values into the shader. Signed-off-by: Dave Airlie <[email protected]>
* r600/shader: add utility functions to do single slot arithmaticDave Airlie2015-12-071-0/+95
| | | | | | | | | These utilities are to be used to do things like integer adds and multiplies to be used in calculating the LDS offsets etc. It handles CAYMAN MULLO differences as well. Signed-off-by: Dave Airlie <[email protected]>
* r600/eg: workaround bug with tess shader and dynamic GPRs.Dave Airlie2015-12-075-61/+190
| | | | | | | | | | | | When using tessellation on eg/ni chipsets, we must disable dynamic GPRs to workaround a hw bug where the GPU hangs when too many things get queued. This implements something like the r600 code to emit the transition between static and dynamic GPRs, and to statically allocate GPRs when tessellation is enabled. Signed-off-by: Dave Airlie <[email protected]>
* r600/shader: move get_temp and last_instruction helpers upDave Airlie2015-12-071-19/+17
| | | | | | These are required for tess to be used earlier. Signed-off-by: Dave Airlie <[email protected]>
* r600: bind geometry shader ring to the correct placeDave Airlie2015-12-071-2/+9
| | | | | | | When tess/gs are enabled, the geom shader ring needs to bind to the tess eval not the vertex shader. Signed-off-by: Dave Airlie <[email protected]>
* r600: create fixed function tess control shader fallback.Dave Airlie2015-12-073-1/+46
| | | | | | | If we have no tess control shader, then we have to use a fallback one that just writes the tessellation factors. Signed-off-by: Dave Airlie <[email protected]>
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