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* radeon/llvm: Remove SILowerShaderInstructions.cppTom Stellard2012-05-104-81/+0
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* radeonsi/llvm: Move lowering of RETURN to ConvertToISA passTom Stellard2012-05-102-11/+2
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* radeon/llvm: Add some commentsTom Stellard2012-05-1064-422/+393
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* radeon/llvm: Move util functions into AMDGPU namespaceTom Stellard2012-05-103-39/+37
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* radeon/llvm: Auto-encode RAT_WRITE_CACHELESS_egTom Stellard2012-05-102-17/+0
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* radeon/llvm: Delete all instructions that have been custom loweredTom Stellard2012-05-101-4/+1
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* radeonsi: Set NONE format for unused vertex shader position export slots.Michel Dänzer2012-05-101-3/+3
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* radeonsi: Eliminate one more magic number for texture image resources.Michel Dänzer2012-05-101-3/+3
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* radeonsi: Fix vertex buffer resource for stride 0.Michel Dänzer2012-05-101-1/+5
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* radeon/llvm: Remove AMDGPUConstants.pmTom Stellard2012-05-092-45/+23
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* radeon/llvm: Don't rely on tablegen for lowering int_AMDGPU_load_constTom Stellard2012-05-095-38/+20
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* radeon/llvm: Make sure the LOAD_CONST def uses the isSI predicateTom Stellard2012-05-092-7/+7
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* svga: implement CEIL opcode translationBrian Paul2012-05-091-0/+28
| | | | Reviewed-by: José Fonseca <[email protected]>
* gallium/drivers: handle TGSI_OPCODE_CEILChristoph Bumiller2012-05-094-0/+28
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* r600g: Handle TGSI_OPCODE_CEIL (v2)Kai Wasserbäch2012-05-091-3/+3
| | | | | | | v2: Enabled CEIL on Cayman too. Signed-off-by: Kai Wasserbäch <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: Remove AMDILUtilityFunctions.cppTom Stellard2012-05-0813-1041/+399
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* radeon/llvm: Remove some unused functions from AMDILInstrInfoTom Stellard2012-05-082-164/+0
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* radeon/llvm: Add some comments and fix coding styleTom Stellard2012-05-088-42/+41
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* radeon/llvm: Remove the EXPORT_REG instructionTom Stellard2012-05-0810-117/+8
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* radeon/llvm: Use a custom inserter to lower RESERVE_REGTom Stellard2012-05-0810-27/+83
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* radeon/llvm: Use a custom inserter to lower STORE_OUTPUTTom Stellard2012-05-084-34/+23
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* radeon/llvm: Remove AMDGPULowerShaderInstructions classTom Stellard2012-05-086-86/+4
| | | | It is no longer used.
* radeon/llvm: Use a custom inserter to lower LOAD_INPUTTom Stellard2012-05-084-39/+15
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* radeon/llvm: Remove the ReorderPreloadInstructions passTom Stellard2012-05-089-100/+4
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* radeon/llvm: Remove old comment from AMDIL.hTom Stellard2012-05-081-5/+0
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* radeon/llvm: add suport for cube texturesVadim Girlin2012-05-082-23/+91
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* radeon/llvm: add support for CUBE ALU instructionVadim Girlin2012-05-085-21/+63
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* radeon/llvm: add support for some ALU instructionsVadim Girlin2012-05-084-13/+293
| | | | | | | | Add support for IABS, NOT, AND, XOR, OR, UADD, UDIV, IDIV, MOD, UMOD, INEG, I2F, U2F, F2U, F2I, USEQ, USGE, USLT, USNE, ISGE, ISLT, ROUND, MIN, MAX, IMIN, IMAX, UMIN, UMAX Signed-off-by: Vadim Girlin <[email protected]>
* radeon/llvm: add missing cases for BREAK/CONTINUEVadim Girlin2012-05-082-0/+3
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* radeon/llvm: add support for AHSR/LSHR/LSHL instructionsVadim Girlin2012-05-084-0/+53
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* radeon/llvm: add support for TXQ/TXF/DDX/DDY instructionsVadim Girlin2012-05-085-4/+43
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* radeon/llvm: add support for VertexID, InstanceIDVadim Girlin2012-05-083-0/+50
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* radeon/llvm: fix live-in handling for inputsVadim Girlin2012-05-082-2/+3
| | | | | | Set the input registers as live-in for entry basic block. Signed-off-by: Vadim Girlin <[email protected]>
* radeon/llvm: add support for v4i32Vadim Girlin2012-05-084-5/+20
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* radeon/llvm: fix ABS_i32 instruction loweringVadim Girlin2012-05-081-2/+2
| | | | | | Swap source operands. Signed-off-by: Vadim Girlin <[email protected]>
* radeon/llvm: use integer comparison for IFVadim Girlin2012-05-081-2/+4
| | | | | | | Replacing "float equal to 1.0f" with "int not equal to 0". This should help for further optimization of boolean computations. Signed-off-by: Vadim Girlin <[email protected]>
* radeon/llvm: use bitcasts for integersVadim Girlin2012-05-083-5/+73
| | | | | | | | | We're using float as default type, so basically for every instruction that wants other types for dst/src operands we need to perform the bitcast to/from default float. Currently bitcast produces no-op MOV instruction, will be eliminated later. Signed-off-by: Vadim Girlin <[email protected]>
* r600g: Fix out of tree builds that use the LLVM backendTom Stellard2012-05-071-1/+1
| | | | https://bugs.freedesktop.org/show_bug.cgi?id=49567
* radeon/llvm: Remove references to DebugFlag and isCurrentDebugType()Tom Stellard2012-05-074-22/+3
| | | | | | | These weren't being used at all and they were causing build failures when LLVM was built with NDEBUG defined and mesa was not. https://bugs.freedesktop.org/show_bug.cgi?id=49110
* nv50: handle VP without inputsMarcin Slusarz2012-05-071-0/+11
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* nvc0/ir: allow abs,neg source modifiers with ceil,floor,truncChristoph Bumiller2012-05-061-0/+3
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* nv50/ir/opt: don't lose saturation in tryCollapseChainedMULsChristoph Bumiller2012-05-061-2/+3
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* nvc0/ir: fix lowering of textureGradChristoph Bumiller2012-05-063-12/+13
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* nouveau: fix nouveau_scratch_runout_release bo count underflowChristoph Bumiller2012-05-061-1/+3
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* nv50: fix typo causing NULL-deref in nv50_resource_resolveChristoph Bumiller2012-05-041-1/+1
| | | | Introduced in b328949a37fee7b0f68ed3e068ffc4426c083042.
* nv50/ir: move expansion of IMUL to later stage and handle memory operandsChristoph Bumiller2012-05-044-17/+51
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* nv50: implement stream outputChristoph Bumiller2012-05-0412-33/+468
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* nv50: enable array texturesChristoph Bumiller2012-05-042-3/+4
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* svga: specify 4-byte aligned vertex elementsBrian Paul2012-05-041-1/+2
| | | | | | | We haven't found a case where this is needed, but it would be prudent for some hosts, per Jose. Reviewed-by: José Fonseca <[email protected]>
* r600g/llvm: Mask write of pred_inst in llvm_if()Tom Stellard2012-05-031-0/+1
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