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* r600g,radeonsi: use a fallback in dma_copy instead of failingMarek Olšák2014-03-116-97/+99
| | | | | | v2: - allow byte-aligned DMA buffer copies on Evergreen - fix piglit/texsubimage regression - use the fallback for 3D copies (depth > 1) as well
* radeonsi: small cleanup in get_paramMarek Olšák2014-03-111-4/+2
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: set correct alignment for texture buffers and constant buffersMarek Olšák2014-03-111-3/+2
| | | | | | | I think these are all equivalent to vertex buffer fetches which should be dword-aligned. Scalar loads are also dword-aligned. Reviewed-by: Michel Dänzer <[email protected]>
* r600g, radeonsi: fix primitives-generated query with disabled streamoutMarek Olšák2014-03-1111-49/+87
| | | | | | | | | | | | | | | | | Buffers are disabled by VGT_STRMOUT_BUFFER_CONFIG, but the query only works if VGT_STRMOUT_CONFIG.STREAMOUT_0_EN is enabled. This moves VGT_STRMOUT_CONFIG to its own state. The register is set to 1 if either streamout or the primitives-generated query is enabled. However, the primitives-emitted query is also incremented, so it's disabled by setting VGT_STRMOUT_BUFFER_SIZE to 0 when there is no buffer bound. This fixes piglit: ARB_transform_feedback2/counting with pause EXT_transform_feedback/primgen-query transform-feedback-disabled Reviewed-by: Michel Dänzer <[email protected]>
* r600g,radeonsi: don't add streamout.num_dw_for_end twiceMarek Olšák2014-03-111-2/+4
| | | | | | | | It's already added in need_cs_space. Also don't calculate anything if there are no buffers. Reviewed-by: Michel Dänzer <[email protected]>
* r600g,radeonsi: fix MAX_TEXTURE_3D_LEVELS and MAX_TEXTURE_ARRAY_LAYERS limitsMarek Olšák2014-03-112-6/+11
| | | | | | | | | CB_COLORi_VIEW.SLICE_MAX can be at most 2047. This fixes the maxlayers piglit test. Cc: [email protected] Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: implement fast color clearMarek Olšák2014-03-115-4/+59
| | | | | | This works for both multi-sample and single-sample color buffers. Reviewed-by: Michel Dänzer <[email protected]>
* r600g: move fast color clear code to a common placeMarek Olšák2014-03-113-84/+88
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* r600g,radeonsi: move CMASK register values from r600_surface to r600_textureMarek Olšák2014-03-116-61/+48
| | | | | | | | | | | When doing fast clear for single-sample color buffers for the first time, a CMASK buffer has to be allocated and the CMASK state in all pipe_surfaces referencing the color buffer must be updated. Updating all surfaces is kinda silly, so let's move the values to r600_texture instead. This is only for Evergreen and later. R600-R700 don't have fast clear. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: convert the framebuffer state to atom-basedMarek Olšák2014-03-115-283/+132
| | | | | | | | | | | This looks like r600g. The shared Cayman MSAA code is used here. The real motivation for this is that I need the ability to change values of color registers after the framebuffer state is set. The PM4 state cannot be modified easily after it's generated. With this, I can just change r600_surface::cb_color_xxx and set framebuffer.atom.dirty=true and it's done. Reviewed-by: Michel Dänzer <[email protected]>
* r600g: move cayman MSAA setup to a common placeMarek Olšák2014-03-116-214/+272
| | | | | | I will use this in radeonsi. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: move framebuffer-related state to a new struct si_framebufferMarek Olšák2014-03-115-39/+41
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* r600g,radeonsi: set priorities for relocationsMarek Olšák2014-03-1116-88/+197
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* r300g,uvd,vce: set priorities for relocationsMarek Olšák2014-03-114-11/+24
| | | | This updates all occurences of cs_add_reloc.
* radeon: Fix build.Vinson Lee2014-03-101-1/+1
| | | | | | | | | | | | | | | | Fix build error introduced with commit dfa25ea5cd19d5a050a1c94bd7370a2259b9f007. CC r600_streamout.lo r600_streamout.c:108:6: error: conflicting types for 'r600_set_streamout_targets' void r600_set_streamout_targets(struct pipe_context *ctx, ^ ./r600_pipe_common.h:413:6: note: previous declaration is here void r600_set_streamout_targets(struct pipe_context *ctx, ^ Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76009 Signed-off-by: Vinson Lee <[email protected]>
* gallium: allow setting of the internal stream output offsetZack Rusin2014-03-0711-25/+34
| | | | | | | | | | | | | | | | D3D10 allows setting of the internal offset of a buffer, which is in general only incremented via actual stream output writes. By allowing setting of the internal offset draw_auto is capable of rendering from buffers which have not been actually streamed out to. Our interface didn't allow. This change functionally shouldn't make any difference to OpenGL where instead of an append_bitmask you just get a real array where -1 means append (like in D3D) and 0 means do not append. Signed-off-by: Zack Rusin <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* ilo: add support for PIPE_QUERY_PIPELINE_STATISTICSChia-I Wu2014-03-104-3/+108
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* ilo: add ILO_3D_PIPELINE_WRITE_STATISTICSChia-I Wu2014-03-105-0/+90
| | | | The command writes statistics registers to the specified bo.
* ilo: add some MI commands to GPEChia-I Wu2014-03-104-0/+116
| | | | We will need MI commands that load/store registers.
* ilo: set PIPE_CONTROL_GLOBAL_GTT_WRITE automaticallyChia-I Wu2014-03-102-2/+16
| | | | | Set the flag automatically in gen6_emit_PIPE_CONTROL(), and set it only for GEN6.
* ilo: print a warning when PPGTT is disabledChia-I Wu2014-03-102-0/+20
| | | | | Despite what the PRMs say, the driver appears to work fine when PPGTT is disabled. But at least print a warning in that case.
* ilo: require hardware logical context supportChia-I Wu2014-03-105-12/+12
| | | | The code paths are not tested for a while, and have some known issues.
* ilo: move ring types to winsysChia-I Wu2014-03-106-34/+11
| | | | | It results in less code despite that i915_drm.h specifies the ring type as part of the execution flags.
* ilo: winsys may limit the batch buffer sizeChia-I Wu2014-03-105-4/+12
| | | | | | The maximum batch buffer size is determined at the time of drm_intel_bufmgr_gem_init(). Make sure the pipe driver does not exceed the limit.
* ilo: PIPE_CAP_QUERY_TIMESTAMP may not be supportedChia-I Wu2014-03-102-1/+4
| | | | Reading TIMESTAMP register may fail, depending on both kernel and hardware.
* ilo: rework winsys batch buffer functionsChia-I Wu2014-03-103-16/+11
| | | | | | | | | | | Rename intel_winsys_check_aperture_size() to intel_winsys_can_submit_bo(), intel_bo_exec() to intel_winsys_submit_bo(), and intel_winsys_decode_commands() to intel_winsys_decode_bo(). Make a semantic change to ignore intel_context when the ring is not the render ring.
* ilo: replace bo alloc flags by initial domainsChia-I Wu2014-03-106-14/+16
| | | | | | The only alloc flag is INTEL_ALLOC_FOR_RENDER, which can as well be expressed by specifying the initial write domain. The change makes it obvious that we failed to set INTEL_ALLOC_FOR_RENDER in several places.
* ilo: remove intel_bo_get_size()Chia-I Wu2014-03-102-14/+18
| | | | | | Commit bfa8d21759c5f2b5b0885c696842167bd4c64fee uses it to work around a hardware limitation. But there are other ways to do it without the need for intel_bo_get_size().
* ilo: remove intel_bo_get_virtual()Chia-I Wu2014-03-104-90/+105
| | | | Make the map functions return the pointer directly.
* ilo: rework winsys bo reloc functionsChia-I Wu2014-03-104-8/+13
| | | | | | | | | | | | | Rename intel_bo_emit_reloc() to intel_bo_add_reloc(), intel_bo_clear_relocs() to intel_bo_truncate_relocs(), and intel_bo_references() to intel_bo_has_reloc(). Besides, we need intel_bo_get_offset() only to get the presumed offset afer adding a reloc entry. Remove the function and make intel_bo_add_reloc() return the presumed offset. While at it, switch to gem_bo->offset64 from gem_bo->offset.
* ilo: remove intel_winsys_enable_reuse()Chia-I Wu2014-03-101-2/+0
| | | | It should be an (winsys) implementation detail.
* radeonsi: Use proper member name for deleting export shader PM4 stateMichel Dänzer2014-03-101-0/+2
| | | | | | Fixes double-free with some piglit tests using geometry shaders. Reviewed-by: Marek Olšák <[email protected]>
* r600g: document why texture offset emulation is neededMarek Olšák2014-03-101-1/+2
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* Revert nvc0 part of "nv50: adjust blit_3d handling of ms output textures"Ilia Mirkin2014-03-091-8/+4
| | | | | | | | The nvc0 bits don't appear to work, and I thought I had removed them from the commit. Oops. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.0 10.1" <[email protected]>
* nv50: adjust blit_3d handling of ms output texturesIlia Mirkin2014-03-092-8/+16
| | | | | | | | This fixes some unwanted scaling when the output is multisampled. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Christoph Bumiller <[email protected]> Cc: "10.0 10.1" <[email protected]>
* nouveau: fix fence waiting logic in screen destroyIlia Mirkin2014-03-093-7/+27
| | | | | | | | | | | | nouveau_fence_wait has the expectation that an external entity is holding onto the fence being waited on, not that it is merely held onto by the current pointer. Fixes a use-after-free in nouveau_fence_wait when used on the screen's current fence. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75279 Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Christoph Bumiller <[email protected]> Cc: "9.2 10.0 10.1" <[email protected]>
* nouveau: add valid range tracking to nouveau_bufferIlia Mirkin2014-03-096-0/+47
| | | | | | | | | This logic is borrowed from the radeon code. The transfer logic will only get called for PIPE_BUFFER resources, so it shouldn't be necessary to worry about them becoming render targets. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Christoph Bumiller <[email protected]>
* radeonsi: fix freeing descriptor buffersChristian König2014-03-081-1/+1
| | | | | | | | That structure member is a pointer, so the loop with the Elements macro only freed up the first entry. Signed-off-by: Christian König <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: fix leaking the bound state on destruction v2Christian König2014-03-083-0/+10
| | | | | | | v2: rebased on stale pointer fixes Signed-off-by: Christian König <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: avoid stale state pointersChristian König2014-03-081-9/+3
| | | | | Signed-off-by: Christian König <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: avoid stale pointers in si_delete_shader_selectorChristian König2014-03-081-1/+6
| | | | | Signed-off-by: Christian König <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeon/vce: fix memory leakChristian König2014-03-081-0/+1
| | | | | Signed-off-by: Christian König <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeon: Include radeon_elf_util.c in the list of LLVM_C_FILES v2Tom Stellard2014-03-072-1/+2
| | | | | | | | | | | | | | | | | This fixes the a build breakage caused by 6974eb907600b9d0176d3158ff0fd30ac3e56a55 on build configurations where all the following are true: 1. radeonsi is not being built 2. r600g is being built 3. opencl is disabled 4. --enable-r600-llvm-compiler is not being used 5. libelf is not installed v2: - Add $(RADEON_CFLAGS) to libllvmradeon_la_CFLAGS Tested-by: Brian Paul <[email protected]>
* radeon/llvm: Factor elf parsing code out into its own functionTom Stellard2014-03-074-51/+132
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeon: Rename struct radeon_llvm_binary to radeon_shader_binary v2Tom Stellard2014-03-075-12/+23
| | | | | | | | | | And move its definition into r600_pipe_common.h; This struct is a just a container for shader code and has nothing to do with LLVM. v2: - Drop unrelated Makefile change Reviewed-by: Michel Dänzer <[email protected]>
* gallium: rename R4A4 and A4R4 formats to match their swizzleMarek Olšák2014-03-071-1/+1
| | | | | | Like L4A4. Reviewed-by: Brian Paul <[email protected]>
* radeonsi: fix blit compressed texture workaround to support 2D arraysMarek Olšák2014-03-071-1/+2
| | | | | | We don't have a piglit test for this, but I think it's correct. Reviewed-by: Michel Dänzer <[email protected]>
* r600g: fix blitting the last 2 mipmap levels for EvergreenMarek Olšák2014-03-073-13/+36
| | | | | | | | This fixes a lot of compressedteximage piglit tests. R600-R700 don't have this issue. Cc: [email protected]
* r600g: fix texelFetchOffset GLSL functionsMarek Olšák2014-03-071-10/+77
| | | | Cc: [email protected]
* radeon: Use upload manager for buffer downloadsNiels Ole Salscheider2014-03-071-18/+56
| | | | | | | Using DMA for reads is much faster. Signed-off-by: Niels Ole Salscheider <[email protected]> Signed-off by: Marek Olšák <[email protected]>
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