Commit message (Collapse) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | radeonsi/gfx9: don't write mipmap level offsets to BO metadata | Marek Olšák | 2017-03-30 | 1 | -3/+6 |
| | | | | | | GFX9 doesn't have (usable) mipmap offsets. Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: flush CB & DB caches with an EOP TS event | Marek Olšák | 2017-03-30 | 1 | -23/+84 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: use ACQUIRE_MEM | Marek Olšák | 2017-03-30 | 1 | -6/+17 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: only use CE RAM for most-used descriptors | Marek Olšák | 2017-03-30 | 2 | -5/+23 |
| | | | | | | because the CE RAM size decreased to 4 KB. Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: emit FLUSH_DFSM where required | Marek Olšák | 2017-03-30 | 2 | -0/+18 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: emit BREAK_BATCH in emit_framebuffer_state | Marek Olšák | 2017-03-30 | 1 | -0/+5 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: fix MIP0_WIDTH & MIP0_HEIGHT for compressed texture blits | Marek Olšák | 2017-03-30 | 6 | -10/+26 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: fix textureSize/imageSize for 1D textures | Marek Olšák | 2017-03-30 | 1 | -25/+32 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: add a workaround for 1D depth textures | Marek Olšák | 2017-03-30 | 3 | -23/+81 |
| | | | | | | The same workaround is used by Vulkan. Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: enable clamping for Z UNORM formats promoted to Z32F | Marek Olšák | 2017-03-30 | 1 | -1/+11 |
| | | | | | | so that shaders don't have to do it. Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: image descriptor changes in mutable fields | Marek Olšák | 2017-03-30 | 3 | -23/+73 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: FMASK image descriptor changes | Marek Olšák | 2017-03-30 | 1 | -21/+48 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: image descriptor changes in immutable fields | Marek Olšák | 2017-03-30 | 2 | -5/+54 |
| | | | | | | | The border color swizzle logic was copied from Vulkan. It doesn't make any sense to me, but it passes all piglits except the stencil ones. Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: DB changes | Marek Olšák | 2017-03-30 | 2 | -94/+176 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: CB changes | Marek Olšák | 2017-03-30 | 2 | -52/+125 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: do DCC clears on non-mipmapped textures only | Marek Olšák | 2017-03-30 | 2 | -4/+17 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: update can_sample_z/s flags | Marek Olšák | 2017-03-30 | 1 | -2/+7 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: pass correct parameters to buffer_get_handle | Marek Olšák | 2017-03-30 | 1 | -6/+14 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: update si_set_optimal_micro_tile_mode | Marek Olšák | 2017-03-30 | 1 | -6/+38 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: don't check array_mode for allowing TC-compatible HTILE | Marek Olšák | 2017-03-30 | 1 | -1/+2 |
| | | | | | | GFX9 supports this with all modes except linear. Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: update HTILE/CMASK/FMASK allocators | Marek Olšák | 2017-03-30 | 1 | -1/+15 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: stub testdma - array_mode_to_string | Marek Olšák | 2017-03-30 | 1 | -12/+18 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: update r600_print_texture_info | Marek Olšák | 2017-03-30 | 3 | -5/+65 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | gallium/radeon: move pre-GFX9 radeon_bo_metadata.* to u.legacy.* | Marek Olšák | 2017-03-30 | 3 | -45/+57 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | gallium/radeon: add GFX9 surface info to radeon_surf | Marek Olšák | 2017-03-30 | 1 | -0/+38 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | gallium/radeon: move pre-GFX9 radeon_surf.* members to radeon_surf.u.legacy.* | Marek Olšák | 2017-03-30 | 18 | -294/+305 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: allow Z16_UNORM for TC-compatible HTILE | Marek Olšák | 2017-03-30 | 1 | -6/+16 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: draw changes | Marek Olšák | 2017-03-30 | 1 | -12/+31 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: pad shader binaries by 128 bytes | Marek Olšák | 2017-03-30 | 1 | -0/+6 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: trivial shader and ring changes | Marek Olšák | 2017-03-30 | 1 | -5/+15 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: sampler state changes | Marek Olšák | 2017-03-30 | 1 | -1/+1 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: add a scissor bug workaround | Marek Olšák | 2017-03-30 | 1 | -0/+6 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: rasterizer changes | Marek Olšák | 2017-03-30 | 1 | -2/+4 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: disable the 2-bit format fetch fix | Marek Olšák | 2017-03-30 | 1 | -2/+6 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: set NUM_RECORDS correctly | Marek Olšák | 2017-03-30 | 3 | -3/+3 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: ELEMENT_SIZE change | Marek Olšák | 2017-03-30 | 2 | -7/+15 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: enable ETC2 | Marek Olšák | 2017-03-30 | 1 | -1/+2 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: disable RB+ on Vega10 | Marek Olšák | 2017-03-30 | 6 | -22/+39 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: init_config changes | Marek Olšák | 2017-03-30 | 1 | -6/+32 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: don't set PA_SC_RASTER_CONFIG* | Marek Olšák | 2017-03-30 | 1 | -15/+19 |
| | | | | | | The registers don't exist on GFX9. Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: Gather4 no longer needs the workaround | Marek Olšák | 2017-03-30 | 1 | -1/+2 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: CP DMA changes | Marek Olšák | 2017-03-30 | 1 | -10/+30 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: query changes - EVENT_WRITE and SET_PREDICATION | Marek Olšák | 2017-03-30 | 1 | -10/+19 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: EVENT_WRITE_EOP -> RELEASE_MEM | Marek Olšák | 2017-03-30 | 1 | -14/+25 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: INDIRECT_BUFFER change | Marek Olšák | 2017-03-30 | 1 | -1/+1 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: enable SDMA buffer copying & clearing | Marek Olšák | 2017-03-30 | 1 | -3/+4 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: handle GFX9 in a few places | Marek Olšák | 2017-03-30 | 4 | -2/+5 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: don't read back non-existent SRBM registers | Marek Olšák | 2017-03-30 | 1 | -3/+5 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: add IB parser support | Marek Olšák | 2017-03-30 | 1 | -0/+1 |
| | | | | | | | | | Both GFX6 and GFX9 fields are printed next to each other in parsed IBs. The Python script parses both headers like one stream and tries to merge all definitions. Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: set the LLVM processor, require LLVM 5.0 | Marek Olšák | 2017-03-30 | 1 | -0/+2 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> |