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* gallium/ilo: cleanup intel_winsys.hEmil Velikov2014-08-283-3/+312
| | | | | | | | | | | | | | | | Make the header location, inclusion and contents more common with its i915,r* and nouveau counterparts: - Move the header within drivers/ilo. - Separate out intel_winsys_create_for_fd into 'drm_public' header. - Cleanup the compiler includes. v2: Move the header to drivers/ilo. Suggested by Chia-I. v3: Correct intel_winsys.h inclusion. Spotted by Chia-I. Cc: Chia-I Wu <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Chia-I Wu <[email protected]>
* gallium: add cap for MAX_VERTEX_ATTRIB_STRIDETimothy Arceri2014-08-2713-0/+32
| | | | | Signed-off-by: Timothy Arceri <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* draw: fix base instance handling in llvm pathRoland Scheidegger2014-08-282-2/+2
| | | | | | | | | | | | | The base instance needs to be passed to the jited function, otherwise the instanced data fetch will only work with the same start instance when the jit function was created (and baking that into the key instead is not a viable option). This fixes piglit arb_base_instance-drawarrays (modulo some unrelated core/compat context trouble I get for the test). And fix the pipe cap bit in llvmpipe for it now that it actually works (it already worked for softpipe). Reviewed-by: Jose Fonseca <[email protected]>
* radeon/uvd: remove comment about RV770Alex Deucher2014-08-271-1/+0
| | | | | | | It doesn't seem to support field based decode after testing. Signed-off-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/uvd: fix field handling on R6XX style UVDChristian König2014-08-261-2/+5
| | | | | | The first UVD generation can only do frame based output. Signed-off-by: Christian König <[email protected]>
* ilo: use genhw command opcodesChia-I Wu2014-08-265-134/+184
| | | | | Replace ILO_GPE_MI and ILO_GPE_CMD with magic values by descriptive genhw macros.
* ilo: rename intel_bo_map_unsynchronized()Chia-I Wu2014-08-262-9/+8
| | | | Rename it to intel_bo_map_gtt_async().
* ilo: remove max_batch_sizeChia-I Wu2014-08-263-8/+1
| | | | | It is used to derive an artificial limit on max relocs per bo. We choose not to export it anymore.
* ilo: replace domains by reloc flagsChia-I Wu2014-08-269-93/+47
| | | | | It is simpler and is supported by the kernel. It cannot be used with libdrm_intel yet though.
* radeonsi: handle PIPE_BIND_BLENDABLEMarek Olšák2014-08-251-1/+5
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* r600g: only set PIPE_BIND_BLENDABLE if colorbuffer rendering is supportedMarek Olšák2014-08-252-20/+10
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* r300g: handle PIPE_BIND_BLENDABLEMarek Olšák2014-08-251-1/+44
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* vc4: Stop doing qpu_inst(add, NOP) or qpu_inst(NOP, mul).Eric Anholt2014-08-241-84/+47
| | | | | Now that the extra WADDR is set, we can knock this off. Saves a lot of typing, and makes this code much more legible.
* vc4: Set the other WADDR in the qpu instruction helpers.Eric Anholt2014-08-241-1/+5
| | | | | Now you don't need to qpu_inst() your instruction with a NOP to get the other waddr set.
* vc4: Merge qpu_a_NOP() and qpu_m_NOP to a single qpu_NOP() helper.Eric Anholt2014-08-243-57/+45
| | | | | | Now that qpu_inst() ignores the WADDR from the other half of the instruction, we can set both the ADD and MUL WADDRs in the NOP helper. Thanks to that, we also no longer need to qpu_inst(NOP, NOP).
* vc4: Ignore WADDRs from the other half of the instruction when merging.Eric Anholt2014-08-241-1/+2
| | | | | | This allows setting the opposite-side WADDR to NOP (a non-zero value) in qpu_* helpers, so that we don't need to qpu_inst() merge them with NOPs all the time just to get the waddr set.
* vc4: Fix LT/GE set-0-or-1 compares.Eric Anholt2014-08-241-1/+1
| | | | | We were using the integer sub, which worked for the common case of EQ and NE. Fixes fs-lessThan-ivec2-ivec2 and other tests.
* freedreno/a2xx: fix segfaultRob Clark2014-08-241-0/+1
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: handle first/last level properlyRob Clark2014-08-243-9/+13
| | | | | | Fixes some assumptions about first_level being zero. Signed-off-by: Rob Clark <[email protected]>
* freedreno: implement pipe_flush_resource()Rob Clark2014-08-241-1/+5
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: don't ignore src/dst levelRob Clark2014-08-241-39/+63
| | | | | | Don't ignore src/dst_level in pipe_copy_region. Signed-off-by: Rob Clark <[email protected]>
* vc4: Fix save/restore of the VS/FS in the blitter.Eric Anholt2014-08-231-2/+2
| | | | | | When I made the shader cache take the .fs member and moved the binding point to .bind_fs, I failed to update these. Fixes crashes in copyteximage-related tests.
* vc4: Clear padding of ioctl arguments.Eric Anholt2014-08-231-0/+1
| | | | Fixes valgrind complaints from valgrind being unaware of our ioctls.
* vc4: Add support for fragment discards.Eric Anholt2014-08-224-0/+43
| | | | | | Fixes piglit glsl-fs-discard-01 and -03, and allows a lot of mesa demos to start running. glsl-fs-discard-02 has a problem where the first tile is not getting stored on the first render.
* vc4: Make some helpers for setting condition codes in instructions.Eric Anholt2014-08-223-15/+27
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* vc4: Avoid using undefined values when there's no color write.Eric Anholt2014-08-221-8/+27
| | | | | | The simulator assertion fails when you read-before-write a temporary value, and there's no point in doing the packing if there was no color written.
* vc4: Emit the scoreboard wait just when it's needed.Eric Anholt2014-08-221-2/+25
| | | | | | | This should improve performance on real hardware by allowing more shader instances to run in parallel. It also fixes assertion failures in tests that don't emit a fragment color, since otherwise we didn't have enough instructions to fit our signals in.
* vc4: Fix FLR for integer values less than 0.Eric Anholt2014-08-221-1/+7
| | | | | | | If we didn't truncate at all, then we don't need to fix for truncation happening in the wrong direction. Fixes piglit builtin-functions/*-floor-*
* vc4: Fix totally broken assertions about inter-instruction reg conflicts.Eric Anholt2014-08-221-3/+18
| | | | | | | | | The spec citation talked about A and B, and I proceeded to pay no attention to whether the waddrs were for A or B. As a result, this pair of instructions would claim to conflict: mov ra4, ra4 ; nop nop, r0, r0 mov.ns ra4, rb4 ; nop nop, r0, r0
* vc4: Add support for all the texture and FBO formats we can.Eric Anholt2014-08-227-72/+203
| | | | | | | Now that tiling is in place, we can expose the other formats. Depth is still broken (need to make changes in the shader), but if you don't expose it things crash all over. SNORM is dropped, but we could re-add it later with some shader fixes to handle converting between [0,1] and [-1,1].
* vc4: Add support for texture tiling.Eric Anholt2014-08-2210-53/+626
| | | | | | This still treats everything as RGBA8888 for the most part, same as before. This is a prerequisite for handling other texture formats, since only RGBA8888 has a raster-layout mode.
* vc4: Fix a typo in the validation for miplevels.Eric Anholt2014-08-221-1/+1
| | | | | | It meant that LUMALPHA was being marked as *many* miplevels, and unsurprisingly wouldn't validate. On the other hand, some miplevel counts wouldn't get the small mips validated at all.
* vc4: Convert to using an enum for texture data typesEric Anholt2014-08-222-20/+43
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* vc4: Stop complaining about unknown texture channel types.Eric Anholt2014-08-221-10/+0
| | | | | It doesn't matter to this code -- the sampler always returns 8-bit unorm rgba.
* vc4: Include stdio/stdlib in headers so I don't have to include it per file.Eric Anholt2014-08-2215-21/+4
| | | | | There are a few tools I want to have always available, and fprintf() and abort() are among them.
* llvmpipe: change LP_MAX_SHADER_INSTRUCTIONS definitionRoland Scheidegger2014-08-211-1/+1
| | | | | | | | | | | | | This change will double cache size for branches which have a lower LP_MAX_SHADER_VARIANTS limit (it will not do anything on master). The reason is that nowadays shaders tend to be quite a bit larger than they were (they were big when llvmpipe didn't have a fs loop, got much smaller with that loop, and since then have gradually increased quite a bit though still smaller than without the fs loop for various reasons - among them being d3d10 compliance, usage of 8-wide vectors, non-swizzled blend code). Thus effectively less shaders would be cached (unless they were very small and the variant limit was hit first). Also, since we're getting rid of the IR nowadays, the cached shaders shouldn't need all that much memory actually.
* r600g: Fix flat/smooth shade state toggle10.3-branchpointGlenn Kennard2014-08-211-1/+3
| | | | | | | | | | | | | If only the flat/smooth shade state changed between two render calls the prior code would miss updating the hardware state. Also add check for sprite coord, potentially same type of issue otherwise for it. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=81967 Signed-off-by: Glenn Kennard <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* r600g/compute: Don't initialize vertex_buffer_state masks to 0x2Tom Stellard2014-08-211-3/+0
| | | | | | | | | | | | | | cs_vertex_buffer_state.enabled_mask and cs_vertex_buffer_state.dirty_mask are both updated when r600_set_constant_buffer() is called, so we don't need to manually update these values. This fixes a crash with OpenCL programs that have a kernel with no arguments. https://bugs.freedesktop.org/show_bug.cgi?id=82671 CC: "10.2" <[email protected]>
* r600g/compute: Use the first parameter in evergreen_set_global_binding()Tom Stellard2014-08-211-2/+3
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* radeon: Add work-around for missing Hainan support in clang < 3.6 v2Tom Stellard2014-08-211-1/+14
| | | | | | | | | v2: - Add missing break. https://bugs.freedesktop.org/show_bug.cgi?id=82709 CC: "10.2" <[email protected]>
* r300g: Fix path to test programs for out-of-tree buildsMichel Dänzer2014-08-202-1/+2
| | | | | | Fixes make check in that case. Reviewed-by: Tom Stellard <[email protected]>
* vc4: Plumb the texture index from TGSI through to the sampler uniforms.Eric Anholt2014-08-191-15/+11
| | | | | This commit and the last one fix ARB_fragment_program/sparse-samplers and 6 other tests.
* vc4: Avoid a null-deref if a sampler index isn't used.Eric Anholt2014-08-191-2/+5
| | | | Part of fixing ARB_fragment_program/sparse-samplers
* r600g: Fix missing SET_TEXTURE_OFFSETSGlenn Kennard2014-08-194-57/+87
| | | | | | | | | | | | SB needs a bit of special handling to handle instructions without obvious side effects, to avoid it deleting them. Fixes failing non-const ARB_gpu_shader5 textureOffsets piglits with sb enabled. Signed-off-by: Glenn Kennard <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* llvmpipe/softpipe: enable ARB_conditional_render_invertedTobias Klausmann2014-08-192-2/+3
| | | | | | Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Tobias Klausmann <[email protected]>
* nvc0: Handle ARB_conditional_render_inverted and enable itTobias Klausmann2014-08-194-32/+37
| | | | | Reviewed-by: Ilia Mirkin <[email protected]> Signed-off-by: Tobias Klausmann <[email protected]>
* gallium: Add and handle PIPE_CAP_CONDITIONAL_RENDER_INVERTEDTobias Klausmann2014-08-1913-0/+15
| | | | | | Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Tobias Klausmann <[email protected]>
* ilo: fix PIPE_CAP_VIDEO_MEMORYChia-I Wu2014-08-191-2/+2
| | | | | | I changed Emil's patch in f921131a5cebc233749a86cdd44b409c0cecc4ef to report raw values in the winsys, but forgot to convert the values to megabytes in the pipe driver.
* ilo: enable HiZ in more cases on GEN6Chia-I Wu2014-08-193-31/+44
| | | | | With layer offsetting killed, we no longer need to restrict HiZ to non-mipmapped and non-arary depth buffers.
* ilo: remove layer offsettingChia-I Wu2014-08-197-393/+27
| | | | Follow i965 to kill layer offsetting for GEN6.
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