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path: root/src/gallium/drivers
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* llvmpipe: handle shader sample mask outputRoland Scheidegger2017-10-181-2/+24
* meson: Add support for the vc5 driver.Eric Anholt2017-10-171-0/+65
* meson: Add support for the vc4 driver.Eric Anholt2017-10-171-0/+101
* radeonsi: if there's just const buffer 0, set it in place of CONST/SSBO pointerMarek Olšák2017-10-174-13/+87
* ac: clean up ac_build_indexed_load function interfacesMarek Olšák2017-10-172-19/+19
* radeonsi: handle 64-bit loads earlier in fetch_constantMarek Olšák2017-10-171-16/+10
* radeonsi: add si_descriptors::gpu_address and remove buffer_offsetMarek Olšák2017-10-173-14/+18
* radeonsi: unify code for extracting a buffer address from a descriptorMarek Olšák2017-10-171-4/+7
* radeonsi: remove atom parameter from si_upload_descriptorsMarek Olšák2017-10-171-8/+4
* radeonsi: pack si_descriptors better againMarek Olšák2017-10-171-2/+2
* radeonsi: emit dirty consecutive pointers in one SET_SH_REG packetMarek Olšák2017-10-171-27/+39
* radeonsi: split si_emit_shader_pointerMarek Olšák2017-10-171-11/+23
* radeonsi: generalize the SI_VS_SHADER_POINTER_MASK macroMarek Olšák2017-10-173-4/+4
* radeonsi/gfx9: use SPI_SHADER_USER_DATA_COMMONMarek Olšák2017-10-171-13/+13
* radeonsi/gfx9: move RW_BUFFERS from s[0:1] to s[8:9] for HS and GSMarek Olšák2017-10-172-39/+16
* radeonsi: add GFX-IB-size query to the HUDMarek Olšák2017-10-173-0/+6
* broadcom/vc4: Fix false-positive for the tiling ioctls on simulator mode.Eric Anholt2017-10-171-0/+1
* broadcom/vc4: Skip BO labeling when in simulator mode.Eric Anholt2017-10-172-1/+5
* broadcom/vc5: Don't forget to set the RT format for 1555 textures.Eric Anholt2017-10-171-2/+2
* meson: build llvmpipeDylan Baker2017-10-161-0/+116
* meson: build softpipeDylan Baker2017-10-161-0/+85
* meson: build nouveau (gallium) driverDylan Baker2017-10-161-0/+224
* meson: build radeonsi gallium driverDylan Baker2017-10-161-1/+1
* meson: build radeonsiDylan Baker2017-10-162-0/+133
* meson: build gallium helper driversDylan Baker2017-10-164-0/+112
* svga: format the version string like the rest of mesaEric Engestrom2017-10-161-5/+5
* svga: fix format_conversion_table breakageBrian Paul2017-10-161-2/+7
* a2xx: add support for a few 16-bit color rendering formatsIlia Mirkin2017-10-152-1/+11
* freedreno/a20x: Enable rendering to RGBA/RGBXWladimir J. van der Laan2017-10-151-1/+3
* freedreno/a20x: Fix rendering to BGRXWladimir J. van der Laan2017-10-151-0/+1
* etnaviv: rework TS enable to be a derived stateLucas Stach2017-10-143-5/+43
* etnaviv: skip unused vertex attributes when assigning VS inputsLucas Stach2017-10-141-0/+4
* broadcom/vc5: Remove the u_resource_vtbl usage.Eric Anholt2017-10-123-25/+18
* radeonsi: implement sync_file import/exportMarek Olšák2017-10-122-2/+79
* winsys/amdgpu: implement sync_file import/exportMarek Olšák2017-10-121-0/+12
* ac: add radeon_info::has_sync_filecros-mesa-17.2.3-vanillachadv/cros-mesa-17.2.3-vanillaMarek Olšák2017-10-121-0/+1
* gallium: add pipe_screen::check_resource_capabilityMarek Olšák2017-10-124-0/+57
* etnaviv: Do GC3000 resolve-in-place when possibleWladimir J. van der Laan2017-10-124-4/+25
* radeonsi: add support for PIPE_FORMAT_{X1,A1}R5G5B5_UNORMNicolai Hähnle2017-10-121-0/+8
* swr: simd16 shaders work in progressTim Rowley2017-10-113-2/+21
* nv50,nvc0: fix push hint logic in presence of a start offsetIlia Mirkin2017-10-112-7/+5
* Android: fix build break from r600/radeon splitRob Herring2017-10-102-1/+5
* r600: cleanup llvm ir target selection.Dave Airlie2017-10-111-18/+2
* r600: drop tc_L2_dirty bit, this was SI only.Dave Airlie2017-10-113-15/+0
* radeonsi: lower ffma in nir to mad.Dave Airlie2017-10-111-0/+1
* broadcom/vc5: Fix handling of 5551 textures using the new gallium format.Eric Anholt2017-10-101-2/+2
* broadcom/vc5: Set the RCL's MSAA mode to match the BCL's MSAA state.Eric Anholt2017-10-101-0/+2
* braodcom/vc5: Set up clear color for higher-bpp formats.Eric Anholt2017-10-101-4/+25
* broadcom/vc5: Set up per-MRT clear colors.Eric Anholt2017-10-103-41/+22
* broadcom/vc5: Fix blendfactor zero handling.Eric Anholt2017-10-101-0/+1
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