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* nvc0/ir: limit max number of regs based on availability in SMIlia Mirkin2016-05-302-2/+4
* nv50/ir: record number of threads in a compute shaderIlia Mirkin2016-05-305-2/+10
* nv50/ir: Add missing handling of U64/S64 in inlinesPierre Moreau2016-05-301-1/+3
* vc4: Fix doxygen warnings12.0-branchpointRhys Kidd2016-05-302-6/+6
* nvc0/ir: fix emission of predicate spill to registerIlia Mirkin2016-05-301-1/+2
* nvc0: fix some compute texture validation bits on keplerIlia Mirkin2016-05-303-2/+7
* swr: automake: silence the python invocationEmil Velikov2016-05-301-7/+8
* swr: automake: attempt to fix the out-of-tree buildEmil Velikov2016-05-301-0/+7
* swr: remove LLVM dependency from source generation rules.Emil Velikov2016-05-301-2/+2
* swr: add all the generators to the release tarball.Emil Velikov2016-05-301-0/+24
* softpipe: add sp_buffer.h to the sources list (release tarball)Emil Velikov2016-05-301-0/+1
* freedreno: make sure we pick up ir3_nir_trig.py in the release tarballEmil Velikov2016-05-301-0/+1
* gallium: push offset down to driverStanimir Varbanov2016-05-302-0/+13
* radeonsi: Don't offset OFFCHIP_BUFFERING on pre-VI cards.Bas Nieuwenhuizen2016-05-301-2/+6
* nv50,nvc0: fix the max_vertices=0 caseIlia Mirkin2016-05-293-2/+4
* swr: [rasterizer] Do not define _mm256_storeu2_m128i with icc.Vinson Lee2016-05-281-1/+1
* gk110/ir: fix unspilling of predicates from registersIlia Mirkin2016-05-281-0/+28
* nvc0: remove outdated surfaces validation code for GK104Samuel Pitoiset2016-05-281-70/+0
* nvc0: do not always invalidate 3D CBs when using computeSamuel Pitoiset2016-05-281-8/+17
* radeonsi: enable OpenGL 4.3Bas Nieuwenhuizen2016-05-271-0/+4
* nouveau: enable GL 4.3 on kepler/fermiDave Airlie2016-05-281-1/+1
* radeonsi: always reserve output space for tess factorsMarek Olšák2016-05-271-1/+6
* gallium/ddebug: Add passthrough for query_memory_info.Bas Nieuwenhuizen2016-05-271-0/+9
* svga: remove unneeded casts in get_query_result_vgpu9() callsBrian Paul2016-05-271-2/+2
* svga: use MAYBE_UNUSED to silence release-build warningsBrian Paul2016-05-271-7/+4
* nvc0/ir: handle a load's reg result not being used for locked variantsIlia Mirkin2016-05-263-11/+45
* nvc0/ir: avoid generating illegal instructions for compute constbuf loadsIlia Mirkin2016-05-261-1/+2
* util/indices,svga: s/unsigned/enum pipe_prim_type/Brian Paul2016-05-262-2/+4
* svga: s/unsigned/enum pipe_resource_usage/ for buffer usage variablesBrian Paul2016-05-263-3/+3
* svga: s/unsigned/enum pipe_prim_type/ for primitive type variablesBrian Paul2016-05-267-14/+15
* svga: fix test for unfilled triangles fallbackBrian Paul2016-05-263-6/+43
* svga: clean up and improve comments in svga_draw_private.hBrian Paul2016-05-261-4/+8
* svga: fix primitive mode (point/line/tri) test for unfilled primitivesBrian Paul2016-05-262-2/+2
* nvc0: invalidate textures/samplers between 3D and CP on FermiSamuel Pitoiset2016-05-262-0/+27
* compiler: Move glsl_to_nir to libglsl.laJason Ekstrand2016-05-261-1/+1
* radeonsi: Allow TES distribution between shader engines.Bas Nieuwenhuizen2016-05-264-15/+40
* radeonsi: Process multiple patches per threadgroup.Bas Nieuwenhuizen2016-05-261-15/+35
* radeonsi: Add barrier before writing the tess factors.Bas Nieuwenhuizen2016-05-261-0/+6
* radeonsi: Enable dynamic HS.Bas Nieuwenhuizen2016-05-262-5/+16
* radeonsi: Remove LDS layout user SGPR's from TES.Bas Nieuwenhuizen2016-05-263-13/+10
* radeonsi: Use buffer loads and stores for passing data from TCS to TES.Bas Nieuwenhuizen2016-05-261-16/+50
* radeonsi: Store inputs to memory when not using a TCS.Bas Nieuwenhuizen2016-05-263-0/+49
* radeonsi: Add offchip buffer address calculation.Bas Nieuwenhuizen2016-05-261-0/+124
* radeonsi: Add user SGPR for the layout of the offchip buffer.Bas Nieuwenhuizen2016-05-263-4/+20
* radeonsi: Use correct parameter index for LS_OUT_LAYOUT.Bas Nieuwenhuizen2016-05-261-3/+4
* radeonsi: Add buffer load functions.Bas Nieuwenhuizen2016-05-261-0/+114
* radeonsi: Define build_tbuffer_store_dwords earlier to support new users.Bas Nieuwenhuizen2016-05-261-69/+69
* radeonsi: Add offchip tessellation parameters.Bas Nieuwenhuizen2016-05-263-6/+34
* radeonsi: Add buffer for offchip storage between TCS and TES.Bas Nieuwenhuizen2016-05-264-0/+23
* nvc0: allow to monitor MP perf counters with compute shadersSamuel Pitoiset2016-05-262-19/+55
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