summaryrefslogtreecommitdiffstats
path: root/src/gallium/drivers
Commit message (Expand)AuthorAgeFilesLines
* android: enable the radeonsi driverChih-Wei Huang2015-06-091-0/+4
* softpipe/query: force parenthesis around a logical notMartin Peres2015-06-081-1/+1
* radeonsi: Add CIK SDMA supportMichel Dänzer2015-06-087-21/+427
* r600g,radeonsi: Assert that there's enough space after flushingMichel Dänzer2015-06-081-3/+2
* r600g: fix a coverity defect in streamout codeMarek Olšák2015-06-051-1/+1
* tgsi/ureg: don't emit in/out arrays if drivers don't support ranged declarationsMarek Olšák2015-06-0510-0/+13
* llvmpipe: Implement stencil exportRoland Scheidegger2015-06-044-15/+21
* vc4: Don't bother with safe list traversal in CSE.Eric Anholt2015-05-291-1/+1
* vc4: Convert from simple_list.h to list.hEric Anholt2015-05-2919-139/+87
* vc4: Make sure we allocate idle BOs from the cache.Eric Anholt2015-05-291-1/+11
* vc4: Fix return value handling for BO waits.Eric Anholt2015-05-291-12/+15
* radeon/llvm: reset temps_count on deallocationMarek Olšák2015-05-291-0/+1
* radeon/llvm: don't use a static array size for radeon_llvm_context::arrays (v2)Marek Olšák2015-05-292-7/+12
* softpipe: fix offset wrapping calculations (v2)Dave Airlie2015-05-291-78/+68
* vc4: Just stream out fallback IB contents.Eric Anholt2015-05-276-42/+41
* vc4: Don't try to put our dmabuf-exported BOs into the BO cache.Eric Anholt2015-05-271-0/+1
* vc4: Don't forget to make our raster shadow textures non-raster.Eric Anholt2015-05-271-0/+3
* vc4: make vc4_begin_query() return a booleanSamuel Pitoiset2015-05-271-1/+2
* radeonsi: use a switch statement in si_delete_shader_selectorMarek Olšák2015-05-261-6/+13
* radeonsi: use a switch statement in si_shader_selector_keyMarek Olšák2015-05-261-9/+16
* radeonsi: fix scratch buffer setup for geometry shadersMarek Olšák2015-05-261-2/+9
* radeonsi: remove unused cases from si_shader_io_get_unique_indexMarek Olšák2015-05-261-14/+3
* radeonsi: don't count special outputs for the VS export countMarek Olšák2015-05-261-0/+5
* radeonsi: add support for PIPE_CAP_TGSI_TEXCOORDMarek Olšák2015-05-264-15/+13
* gallium: use const in set_tess_stateMarek Olšák2015-05-261-2/+2
* nv30: falling back to draw path for edgeflag does no goodIlia Mirkin2015-05-251-3/+2
* nv30/draw: switch varying hookup logic to know about texcoordsIlia Mirkin2015-05-251-9/+16
* nv30/draw: allocate vertex buffers in gartIlia Mirkin2015-05-251-6/+10
* nv30/draw: only use the DMA1 object (GART) if the bo is not in VRAMIlia Mirkin2015-05-251-3/+3
* nv30/draw: fix indexed draws with swtnl path and a resource index bufferIlia Mirkin2015-05-251-3/+3
* llvmpipe: (trivial) add parantheses in (!x == y) expressionRoland Scheidegger2015-05-251-1/+1
* nv30/draw: draw expects constbuf size in bytes, not vec4 unitsIlia Mirkin2015-05-251-1/+1
* nv30/draw: avoid leaving stale pointers in draw stateIlia Mirkin2015-05-251-4/+4
* nv30: fix clip plane uploads and enable changesIlia Mirkin2015-05-241-9/+7
* nv30: avoid doing extra work on clear and hitting unexpected statesIlia Mirkin2015-05-245-9/+11
* nv30: avoid leaking render state and draw shadersIlia Mirkin2015-05-243-0/+16
* nv30: don't leak fragprog constsIlia Mirkin2015-05-241-0/+1
* nv50/ir: avoid messing up arg1 of PFETCHIlia Mirkin2015-05-231-2/+18
* nv30: check nouveau_bo_map output of notify boIlia Mirkin2015-05-231-1/+1
* nvc0: a geometry shader can have up to 1024 vertices outputIlia Mirkin2015-05-231-1/+1
* nv50: fix PIPE_QUERY_TIMESTAMP_DISJOINT, based on nvc0Samuel Pitoiset2015-05-231-17/+22
* nvc0/ir: LOAD's can't be used for shader inputsIlia Mirkin2015-05-222-0/+2
* nv50/ir: guess that the constant offset is the starting slot of arrayIlia Mirkin2015-05-221-2/+4
* nvc0/ir: set ftz when sources are floats, not just destinationsIlia Mirkin2015-05-221-3/+2
* nv50/ir: allow OP_SET to merge with OP_SET_AND/etc as well as a negIlia Mirkin2015-05-221-26/+55
* nvc0/ir: optimize set & 1.0 to produce boolean-float setsIlia Mirkin2015-05-222-0/+29
* nvc0/ir: allow iset to produce a boolean floatIlia Mirkin2015-05-223-5/+16
* nvc0/ir: avoid jumping to a sched instructionIlia Mirkin2015-05-223-2/+9
* nv50: fix PIPELINE_STATISTICS with HUD, based on nvc0Samuel Pitoiset2015-05-221-1/+2
* nv50: fix 64-bit queries with HUD, based on nvc0Samuel Pitoiset2015-05-221-1/+13