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* radeonsi: remove switch statement in si_create_contextMarek Olšák2015-07-233-13/+7
| | | | | | and make si_init_config static Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: don't change pipe_resource in resource_copy_regionMarek Olšák2015-07-234-160/+110
| | | | | | | Copied from r600g. pipe_resource can be shared by multiple threads, so we shouldn't change it. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: upload shader rodata after updating scratch relocationsMarek Olšák2015-07-233-29/+29
| | | | | | Cc: 10.5 10.6 <[email protected]> Reviewed-by: Tom Stellard <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: remove redundant parameter in si_shader_binary_readMarek Olšák2015-07-233-8/+5
| | | | | Reviewed-by: Tom Stellard <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: Flush when we're asked to return a fence but don't have one yetMichel Dänzer2015-07-221-1/+2
| | | | Reviewed-by: Marek Olšák <[email protected]>
* gallium: replace INLINE with inlineIlia Mirkin2015-07-21182-647/+647
| | | | | | | | | | | | | | | | Generated by running: git grep -l INLINE src/gallium/ | xargs sed -i 's/\bINLINE\b/inline/g' git grep -l INLINE src/mesa/state_tracker/ | xargs sed -i 's/\bINLINE\b/inline/g' git checkout src/gallium/state_trackers/clover/Doxyfile and manual edits to src/gallium/include/pipe/p_compiler.h src/gallium/README.portability to remove mentions of the inline define. Signed-off-by: Ilia Mirkin <[email protected]> Acked-by: Marek Olšák <[email protected]>
* nvc0: force cache flush when binding a new uboSamuel Pitoiset2015-07-211-0/+2
| | | | | | | | This fixes the following piglit test: ext_transform_feedback-immediate-reuse-uniform-buffer Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50: force cache flush when binding a new uboSamuel Pitoiset2015-07-211-0/+2
| | | | | | | | This fixes the following piglit test: ext_transform_feedback-immediate-reuse-uniform-buffer Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* r600/sb: Fix an &/&& mistakeAdam Jackson2015-07-211-1/+1
| | | | | | | | | | | | | | | gcc says: sb/sb_sched.cpp: In member function 'bool r600_sb::alu_group_tracker::try_reserve(r600_sb::alu_node*)': sb/sb_sched.cpp:492:7: warning: suggest parentheses around operand of '!' or change '&' to '&&' or '!' to '~' [-Wparentheses] if (!trans & fbs) It happens to be harmless; if fbs is ever non-zero, it will be VEC_210, which is 5, so (!trans & 5) == 1 and the branch works as expected. But logical AND is clearly what was meant. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Adam Jackson <[email protected]>
* nouveau: use bool instead of booleanSamuel Pitoiset2015-07-2169-678/+678
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Acked-by: Ilia Mirkin <[email protected]>
* nvc0: add a missing parameter to nvc0_set_shader_images()Samuel Pitoiset2015-07-201-3/+3
| | | | | | | | | | | This fixes a compilation warning introduced in commit 05a12c5 (gallium: add interface for writable shader images). While we are at it, fix indentation and rename parameters according to the gallium interface. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nouveau: always align buffers to 0x100Samuel Pitoiset2015-07-201-7/+1
| | | | | | | | | | | | | | Only constbufs must be aligned to 0x100, but since all buffers can be rebinded as constant buffers they must be also aligned. This patch prevents this behaviour by aligning everything to 256-byte increments at buffer creation. This fixes dmesg fails for the following piglit test: ext_transform_feedback-immediate-reuse-uniform-buffer -auto -fbo Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50: limit the maximum number of samplers to 16Samuel Pitoiset2015-07-201-1/+1
| | | | | | | | | | | | | | NV50_3D_BIND_TSC only allows to bind 16 samplers, and since we don't want to do anything with NV50_3D_BIND_TSC2, just limit the maximum number of samplers to 16 like for nvc0. This fixes dmesg fails with the following piglit test: max-samplers But the test still fails. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50: turn samples counts off during blitSamuel Pitoiset2015-07-201-0/+11
| | | | | | | | Fixes the following piglit test: occlusion_query_meta_no_fragments Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50: add nesting support for occlusion queriesSamuel Pitoiset2015-07-202-11/+20
| | | | | | | This is loosely based on nvc0. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50: fix max level clamping on G80Ilia Mirkin2015-07-201-2/+9
| | | | | | | | | It appears that the G80 did not have support for the sampler view first/last clamping. Put the view's last level in the place of the texture's so that it doesn't go past what the sampler view allows. Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* gm107/ir: fix indirect txq emissionIlia Mirkin2015-07-181-2/+8
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* nvc0/ir: don't worry about sampler in txq handlingIlia Mirkin2015-07-181-22/+8
| | | | | | | | | There's no need to deal with samplers for texture size queries. That code also was accidentally setting an invalid sIndirectSrc position, but it can now just be removed. Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* nvc0/ir: fix txq on indirect samplersIlia Mirkin2015-07-182-2/+56
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* vc4: Switch to using a separate ioctl for making shaders.Eric Anholt2015-07-174-12/+78
| | | | | | | | | This gives the kernel a chance to validate and lock down the data, without having to deal with mmap zapping. With this, GLBenchmark stops on a texture relocations, because we'd recycled a shader BO as another shader and failed to revalidate, since we weren't clearing the cached validation state on mmap faults.
* vc4: Fix printing of shader-db debug when shader-db isn't turned on.Eric Anholt2015-07-171-4/+6
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* vc4: Add debugging on texture relocation validation failures.Eric Anholt2015-07-171-7/+13
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* vc4: Also consider uniform 0 in uniform lowering.Eric Anholt2015-07-171-3/+3
| | | | The hash table considers key 0 to be the empty key.
* vc4: Use the pure/const attributes on a bunch of our QPU functions.Eric Anholt2015-07-172-18/+18
| | | | | | On a release build, this makes the rest of vc4_qpu_validate.c go away (the compiler didn't know that our qpu helper function calls had no side effects).
* gallium: add interface for writable shader imagesMarek Olšák2015-07-162-8/+12
| | | | | | PIPE_CAPs will be added some other time. Reviewed-by: Ilia Mirkin <[email protected]>
* gallium: add new limits for shader buffers and imagesMarek Olšák2015-07-161-1/+1
| | | | Reviewed-by: Ilia Mirkin <[email protected]>
* gallium: add BIND flags for R/W buffers and imagesMarek Olšák2015-07-164-4/+6
| | | | | | | | | | | | | | | | | PIPE_CAPs and TGSI support will be added later. The TGSI support should be straightforward. We only need to split TGSI_FILE_RESOURCE into TGSI_FILE_IMAGE and TGSI_FILE_BUFFER, though duplicating all opcodes shouldn't be necessary. The idea is: * ARB_shader_image_load_store should use set_shader_images. * ARB_shader_storage_buffer_object should use set_shader_buffers(slots 0..M-1) if M shader storage buffers are supported. * ARB_shader_atomic_counters should use set_shader_buffers(slots M..N) if N-M+1 atomic counter buffers are supported. PIPE_CAPs can describe various constraints for early DX11 hardware. Reviewed-by: Ilia Mirkin <[email protected]>
* gallium: add PIPE_CAP_MAX_SHADER_PATCH_VARYINGSMarek Olšák2015-07-1613-0/+13
| | | | Reviewed-by: Ilia Mirkin <[email protected]>
* vc4: Cache the texture p1 for the sampler.Eric Anholt2015-07-143-49/+69
| | | | | Cuts another 12% of vc4_uniforms.o, in exchange for computing it at CSO creation time.
* vc4: Cache texture p0/p1 setup for the sampler view.Eric Anholt2015-07-143-28/+43
| | | | | In exchange for a bit of space and computation in CSO setup, we cut vc4_uniform.c (draw time) code size by 4.8%.
* vc4: Move uniforms handling to a separate file.Eric Anholt2015-07-143-314/+341
| | | | | The rest of vc4_program.c is about compiling, while this is about uniform emit at draw time.
* vc4: Fix some -Wdouble-promotion warnings.Eric Anholt2015-07-143-6/+6
| | | | | No code generation changes from this, but it'll be useful to have this next time I go checking -Wdouble-promotion.
* vc4: Fix compiler warnings on release builds.Eric Anholt2015-07-144-7/+14
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* vc4: Add better debug for register allocation failure.Eric Anholt2015-07-141-1/+5
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* vc4: Drop reloc_count tracking for debug asserts on non-debug builds.Eric Anholt2015-07-141-0/+10
| | | | Cuts another 88 bytes of compiled code.
* vc4: Rework cl handling to be friendlier to the compiler.Eric Anholt2015-07-146-152/+203
| | | | | Drops 680 bytes of code, from avoiding a bunch of extra updates to the next pointer in the struct.
* vc4: Make a helper function for getting the current offset in the CL.Eric Anholt2015-07-144-20/+21
| | | | | | I needed to rewrite this a bit for safety checking in the next commit. Despite being a static inline of the same thing that was being done, we lose 36 bytes of code for some reason.
* vc4: Drop separate cl*_reloc_hindex().Eric Anholt2015-07-141-18/+6
| | | | | | Now that RCL generation is in the kernel, we don't have any other callers. Oddly, the compiler generates another 8 bytes of code for this, but the simplification is worth it.
* vc4: Store reloc pointers as pointers, not offsets.Eric Anholt2015-07-141-5/+5
| | | | | | | Now that we don't resize the CL as we build (it's set up at the top by vc4_start_draw()), we can store the pointers instead of offsets from the base. Saves a bit of math in emitting relocs (about 60 bytes of code).
* vc4: Add perf debug for when we wait on BOs.Eric Anholt2015-07-144-43/+72
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* radeonsi: directly include radeon/* headersEmil Velikov2015-07-131-1/+1
| | | | Signed-off-by: Emil Velikov <[email protected]>
* radeonsi: direct emit intrinsic for DFRAC.Dave Airlie2015-07-131-0/+1
| | | | | | Michel reported this still failed, and this fixed it Signed-off-by: Dave Airlie <[email protected]>
* radeonsi: ARB_gpu_shader_fp64 + ARB_vertex_attrib_64bit support.Dave Airlie2015-07-124-11/+171
| | | | | | | | | | | | This adds the translation from TGSI to AMDGPU llvm backend, for the 64-bit opcodes. The backend pretty much handles everything for us fine. There is one patch required for SI DFRAC support, that I know off. [airlied: fixed missing comma, updated relnotes] Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600g: move sampler/ubo index registers before temp regDave Airlie2015-07-111-7/+6
| | | | | | | | | | | temp_reg needs to be last, as we increment things away from it, otherwise on cayman some tests were overwriting the index regs. Fixes 2 piglit with ARB_gpu_shader5 forced on cayman. Reviewed-by: Glenn Kennard <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600g: fix sampler/ubo indexing on caymanDave Airlie2015-07-112-6/+18
| | | | | | | | | | Cayman needs a different method to upload the CF IDX0/1 This fixes 31 piglits when ARB_gpu_shader5 is forced on with cayman. Reviewed-by: Glenn Kennard <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* nv50, nvc0: enable at least one color RT if alphatest is enabledIlia Mirkin2015-07-102-0/+36
| | | | | | | | | Fixes the following piglits: fbo-alphatest-nocolor fbo-alphatest-nocolor-ff Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* freedreno/a4xx: occlusion query supportRob Clark2015-07-101-1/+85
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2015-07-1011-57/+116
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3/sched: fixup new instr's blockRob Clark2015-07-101-0/+4
| | | | | | | | | | | | If we split addr/pred, the original instruction could have originated from a different block. If we don't fixup the block ptr we hit asserts later (in debug builds). NOTE: perhaps we don't want to try to preserve addr/pred reg's across block boundaries.. this at least needs some thought in case addr/pred writes end up inside a conditional block.. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3/ra: fix failed assert for a0/p0Rob Clark2015-07-101-0/+5
| | | | | | | | The address and predicate register are special, they don't get assigned in RA. So do a better job of ignoring them rather than hitting later asserts. Signed-off-by: Rob Clark <[email protected]>
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