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* softpipe: Fix textureLod with nonzero GL_TEXTURE_LOD_BIAS valueKrzesimir Nowak2015-09-101-1/+1
| | | | | | | | | The level-of-detail bias wasn't simply added in the explicit LOD case. This case seems to be tested only in piglit's fs-texturequerylod-nearest-biased test, which is currently skipped, as softpipe does not support textureQueryLod at the moment. Reviewed-by: Brian Paul <[email protected]>
* gallium/radeon: handle PIPE_TRANSFER_FLUSH_EXPLICITMarek Olšák2015-09-103-22/+44
| | | | | | | | Basically, do the same thing as for buffer_unmap, but use the explicit range instead. It's for apps which want to map a whole buffer and mark touched ranges explicitly. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: don't update polygon offset state if it has no effectMarek Olšák2015-09-102-1/+4
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: decrease the size of si_pm4_stateMarek Olšák2015-09-101-3/+2
| | | | Acked-by: Michel Dänzer <[email protected]>
* radeonsi/compute: add buffers to the CS directlyMarek Olšák2015-09-101-7/+11
| | | | | | Packets are emitted immediately anyway. Acked-by: Michel Dänzer <[email protected]>
* radeonsi: only use new versions of LLVM image and sample intrinsicsMarek Olšák2015-09-101-283/+186
| | | | | | | | Just a cleanup I had made a long time ago and forgot about. v2: use tgsi_is_shadow_target Reviewed-by: Tom Stellard <[email protected]>
* gallium/radeon: drop support for LLVM 3.4Marek Olšák2015-09-106-25/+7
| | | | | | This allows using the new tex instrinsics unconditionally. Reviewed-by: Michel Dänzer <[email protected]>
* r600/llvm: remove dead code for LLVM 3.3Marek Olšák2015-09-101-106/+0
| | | | | | LLVM 3.3 has been unsupported for quite a while. Reviewed-by: Michel Dänzer <[email protected]>
* r600g: use pipe_resource::width0 instead pb_buffer::sizeMarek Olšák2015-09-102-6/+6
| | | | | | | | | | | pb_buffer::size was aligned by 29aaab2b5f55cc6d9a84f58ce2bb8607e76a9dde, which broke the CMASK code I think. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91881 Cc: 11.0 <[email protected]> Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: enable VGPR spilling on VIMarek Olšák2015-09-101-3/+1
| | | | | | | This fixes corruption in Unigine Heaven on VI Cc: 11.0 <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* nv50/ir: don't fold immediate into mad if registers are too highIlia Mirkin2015-09-101-0/+4
| | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91551 Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.0" <[email protected]>
* nv50/ir: fix emission of 8-byte wide interp instructionIlia Mirkin2015-09-101-5/+6
| | | | | | | | | This can come up if the target register number is > 63, which is fairly rare. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91551 Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.0" <[email protected]>
* nv50/ir: r63 is only 0 if we are using less than 63 registersIlia Mirkin2015-09-101-1/+4
| | | | | | | | | It is advantageous to use r63 instead of r127 since r63 can fit into the shorter encoding. However if we've RA'd over 63 registers, we must use r127 as the replacement instead. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.0" <[email protected]>
* nv50/ir: make edge splitting fix up phi node sourcesIlia Mirkin2015-09-101-13/+77
| | | | | | | | | | | | | | | | | | | | | Unfortunately nv50_ir phi nodes aren't directly connected to the CFG, so the mapping between source and the actual BB is by inbound edge order. So when manipulating edges one has to be extremely careful. We were insufficiently careful when splitting critical edges which resulted in the phi nodes being confused as to where their sources were coming from. This primarily manifests itself with the TXL-lowering logic on nv50, when it is inside of a conditional. I've been unable to trigger the issue anywhere else so far. This resolves rendering failures in a number of games like Two Worlds 2, Trine: Enchanted Edition, Trine 2, XCOM:Enemy Unknown, Stacking. It also improves the situation in Hearthstone, Sonic Generations, and The Raven: Legacy of a Master Thief. However more work needs to be done there (splitting a lot more edges solves it, so it's some other sort of RA-related issue). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90887 Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.0" <[email protected]>
* nvc0: remove BGRA4 format supportIlia Mirkin2015-09-091-0/+2
| | | | | | | | | | | Something is wrong with the support somewhere. I couldn't get the blob driver to use it either, although it happily used RGB5_A1. teximage-colors works, but WoW seems to fail in the menus for drawing text. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91526 Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.6 11.0" <[email protected]>
* nvc0: keep track of cb bindings per buffer, use for upload settingsIlia Mirkin2015-09-097-12/+58
| | | | | | | | | | | | | | | | | | | CB updates to bound buffers need to go through the CB_DATA endpoints, otherwise the shader may not notice that the updates happened. Furthermore, these updates have to go in to the same address as the bound buffer, otherwise, again, the shader may not notice updates. So we keep track of all the places where a constbuf is bound, and iterate over all of them when updating data. If a binding is found that encompasses the region to be updated, then we use the settings of that binding for the upload. Otherwise we upload as a regular data update. This fixes piglit 'arb_uniform_buffer_object-rendering offset' as well as blurriness in Witcher2. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91890 Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.0" <[email protected]>
* nv30: Disable msaa unless requested from the env by NV30_MAX_MSAAHans de Goede2015-09-092-1/+21
| | | | | | | | | | | | | | | | | | | | Some modern apps try to use msaa without keeping in mind the restrictions on videomem of older cards. Resulting in dmesg saying: [ 1197.850642] nouveau E[soffice.bin[3785]] fail ttm_validate [ 1197.850648] nouveau E[soffice.bin[3785]] validating bo list [ 1197.850654] nouveau E[soffice.bin[3785]] validate: -12 Because we are running out of video memory, after which the program using the msaa visual freezes, and eventually the entire system freezes. To work around this we do not allow msaa visauls by default and allow the user to override this via NV30_MAX_MSAA. Signed-off-by: Hans de Goede <[email protected]> [imirkin: move env var lookup to screen so that it's only done once] Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.6 11.0" <[email protected]>
* nv30: Fix color resolving for nv3x cardsHans de Goede2015-09-091-1/+37
| | | | | | | | | | | | | We do not have a generic blitter on nv3x cards, so we must use the sifm object for color resolving. This commit divides the sources and dest surfaces in to tiles which match the constraints of the sifm object, so that color resolving will work properly on nv3x cards. Signed-off-by: Hans de Goede <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Cc: "11.0" <[email protected]>
* android: radeonsi: add support for sid_tables.h generated sourcesMauro Rossi2015-09-093-3/+15
| | | | | | | | | | This patch is necessary to avoid building error on android, due to missing sid_tables.h generated sources v2:[Emil Velikov] Correctly split the lists. Fixes: fbbebeae10f(radeonsi: inline si_cmd_context_control) Signed-off-by: Emil Velikov <[email protected]>
* nouveau: android: add space before PRIx64 macroMauro Rossi2015-09-091-1/+1
| | | | | | | | | | | | | | | | | | | | | Otherwise the android build fails with error : unable to find string literal operator ‘operator"" PRIx64’ There are several resources referring to the problem, which is related to c++11, in our case used when building mesa for lollipop. http://comments.gmane.org/gmane.comp.graphics.opensg.user/5883 I've not investigated all the semantics, some people even suggested a bug in the gcc compiler, I just saw the building error was solved with one little space for lollipop and no side effect when c+11 not used. v2: [Emil Velikov] add an alternative commit message from Mauro. Cc: 11.0 <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* svga: pick all the files into the tarballEmil Velikov2015-09-091-5/+26
| | | | Signed-off-by: Emil Velikov <[email protected]>
* r600: don't use shader key without verifying shader type (v2)Dave Airlie2015-09-091-7/+12
| | | | | | | | | | | | | | | | | Since 7a32652231f96eac14c4bfce02afe77b4132fb77 r600: Turn 'r600_shader_key' struct into union we were accessing key fields that might be aliased in the union with other fields, so we should check what shader type we are compiling for before using key values from it. v1.1: make it compile v2: have caffeine, make it work - we don't set type until later, so don't reference it until we've set it. Reviewed-by: Edward O'Callaghan <[email protected]> Cc: "11.0" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* nvc0: always emit a full shader colormaskIlia Mirkin2015-09-081-1/+1
| | | | | | | | | | | | | | Indications are that if the colormask indicates a single bit set on fermi, that value will always be read from $r0 instead of a potentially higher register (if e.g. green is set). Not to upset the counting logic, always set the header up with a full color mask for each RT. Such a situation can basically only ever happen with generated blit shaders. Fixes the following piglit on Fermi (Kepler is unaffected): fbo-stencil blit GL_DEPTH32F_STENCIL8 Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.6 11.0" <[email protected]>
* nv30: Fix max width / height checks in nv30 sifm codeHans de Goede2015-09-071-2/+2
| | | | | | | | | | | | | The sifm object has a limit of 1024x1024 for its input size and 2048x2048 for its output. The code checking this was trying to be clever resulting in it seeing a surface of e.g 1024x256 being outside of the input size limit. This commit fixes this. Signed-off-by: Hans de Goede <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Cc: "10.6 11.0" <[email protected]>
* svga: Fix surface view error handlingThomas Hellstrom2015-09-071-22/+26
| | | | | | | | | Make sure errors are correcly propagated. Also don't flush during state emission if emission fails. Signed-off-by: Thomas Hellstrom <[email protected]> Reviewed-by: Charmaine Lee <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* nouveau: don't mark full range as used on unmap with explicit flushIlia Mirkin2015-09-051-5/+7
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* nv50: avoid using inline vertex data submit when gl_VertexID is usedIlia Mirkin2015-09-054-2/+14
| | | | | | | | | | | The hardware only generates vertexid when vertices come from a VBO. This fixes: vertexid-drawelements vertexid-drawarrays Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.0" <[email protected]>
* nv50: don't flush vertex arrays when index buffer changesIlia Mirkin2015-09-051-4/+0
| | | | | | | | The index buffer is fed in inline over a pushbuf. It's not related to vertices or any caching that might be done on them. Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* nv50: rebind bo to bufctx when invalidating idxbuf storageIlia Mirkin2015-09-051-1/+5
| | | | | | | | There is nothing to be done on a dirty idxbuf, but the bo may have changed, so we have to rebind it to the bufctx. Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* nv50: clear buffer status on all vertex bufs, not just the first oneIlia Mirkin2015-09-051-1/+0
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* nv50: fix drawing from tfb, direct-to-pushbuf submitsIlia Mirkin2015-09-054-14/+15
| | | | | | | | | | | The stride was being set to 0, which is illegal (and also non-sensical). Also we must wait for the buffer to become available for reading as otherwise a wrong value may be prefetched. Since we must wait for the buffer anyways, and it's mapped and in GART, we may as well avoid the annoyance of the indirect pushbuf submit. Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* nv30: Implement color resolve for msaaHans de Goede2015-09-042-14/+8
| | | | | | | | | | | Note this is not ideal. Since the sifm can only do source sizes upto 1024x1024 we end up using the blitter on nv4x, which is not that fast. And on nv3x we end up using the cpu which is really slow. Cc: "10.6 11.0" <[email protected]> Signed-off-by: Hans de Goede <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv30: Fix creation of scanout buffersHans de Goede2015-09-041-0/+10
| | | | | | | | | | | | | | | | | | | | | Scanout buffers on nv30 must always be non-swizzled and have special width alignment constraints. These constrains have been taken from the xf86-video-nouveau src/nv_accel_common.c: nouveau_allocate_surface() function. nouveau_allocate_surface() applies these width constraints only when a tiled attribute is set, which it sets for all surfaces allocated via dri, and this "tiling" is not the same as swizzling, scanout surfaces must be linear / have a uniform_pitch or only complete garbage is shown. This commit fixes dri3 on nv30 showing a garbled display, with dri3 the scanout buffers are allocated by mesa, rather then by the ddx, and the wrong stride of these buffers was causing the garbled display. Cc: "10.6 11.0" <[email protected]> Signed-off-by: Hans de Goede <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* vc4: Initialize pack field of qreg to 0 in qir_get_tempBoyan Ding2015-09-041-0/+1
| | | | | | | | | | | | | This avoids generation of undefined packing in qir and qpu instructions, fixing a lot of rendering errors. Fixes 8b36d107fdd (vc4: Pack the unorm-packing bits into a src MUL instruction when possible.) Cc: [email protected] Signed-off-by: Boyan Ding <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* r600: fix loop overrun in cayman_mul_double_instrDave Airlie2015-09-041-1/+1
| | | | | | Coverity warned about this. Ilia pointed it out. Signed-off-by: Dave Airlie <[email protected]>
* svga: update call to u_upload_alloc()Brian Paul2015-09-031-3/+3
| | | | | | u_upload_alloc() no longer returns a return value. Trivial.
* gallium/radeon: remove 'dirty' member from r600_atomGrazvydas Ignotas2015-09-034-6/+1
| | | | | | It's no longer used by both r600 and radeonsi now. Signed-off-by: Marek Olšák <[email protected]>
* r600g: simplify dirty atom trackingGrazvydas Ignotas2015-09-033-49/+14
| | | | | | | Now that R600_NUM_ATOMS is below 64, dirty atom tracking can be simplified. Signed-off-by: Marek Olšák <[email protected]>
* r600g: start numbering atoms from 1Grazvydas Ignotas2015-09-033-3/+3
| | | | | | | There doesn't seem any reason to start from 4. Start from 1 instead (0 is left reserved to catch uninitialized atoms). Signed-off-by: Marek Olšák <[email protected]>
* r600g: make all viewport states use single atomGrazvydas Ignotas2015-09-036-34/+38
| | | | | | | Similarly to scissor states, we can use single atom to track all viewport states. This will allow to simplify dirty atom handling later. Signed-off-by: Marek Olšák <[email protected]>
* r600g: apply disable workaround on all scissorsGrazvydas Ignotas2015-09-032-9/+14
| | | | | | | | During review of the "r600g: make all scissor states use single atom" patch Marek Olšák noticed that scissor disable workaround should be applied on all scissor states and not just first one, so let's do so. Signed-off-by: Marek Olšák <[email protected]>
* r600g: make all scissor states use single atomGrazvydas Ignotas2015-09-036-40/+62
| | | | | | | As suggested by Marek Olšák, we can use single atom to track all scissor states. This will allow to simplify dirty atom handling later. Signed-off-by: Marek Olšák <[email protected]>
* mesa: Fix warning about static being in the wrong placeIan Romanick2015-09-021-1/+1
| | | | | | | | | | | | | | | | | | | | Because the compiler already has enough things to complain about. grep -rl 'const static' src/ | while read f do sed --in-place -e 's/const static/static const/g' $f done brw_eu_emit.c: In function 'brw_reg_type_to_hw_type': brw_eu_emit.c:98:7: warning: 'static' is not at beginning of declaration [-Wold-style-declaration] const static int imm_hw_types[] = { ^ brw_eu_emit.c:120:7: warning: 'static' is not at beginning of declaration [-Wold-style-declaration] const static int hw_types[] = { ^ Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* svga: fix referencing a NULL framebuffer cbufCharmaine Lee2015-09-021-2/+2
| | | | | | | | | Check for a valid framebuffer cbuf pointer before accessing its associated surface. Fix piglit test fbo-drawbuffers-none. Reviewed-by: Brian Paul <[email protected]>
* svga: increment texture age when surface is to be marked as dirtyCharmaine Lee2015-09-021-7/+6
| | | | | | | | | | | | | | | | Commit b9ba8492 removes an unneeded pipe_surface_release() from st_render_texture(). This implies a surface can now be reused for a render buffer. Currently, when we render to a texture, we mark the surface as dirty. But in svga_mark_surface_dirty(), if the surface is already marked as dirty, it does not increment the texture age. Any view to this texture might not be updated properly then. With this patch, the texture age is incremented regardless of whether the surface is already marked as dirty or not. Fix bug 1499181. Reviewed-by: Sinclair Yeh <[email protected]>
* svga: fix backed surface view regressionCharmaine Lee2015-09-024-17/+46
| | | | | | | | | | | | | | | | | | Commit b9ba8492 removes an unneeded pipe_surface_release() from st_render_texture() and exposes a bug in the backed surface view creation. Currently a backed surface view for a conflicted surface view is created at framebuffer emit time. But if shader sampler views are changed but framebuffer surface views remain unchanged, emit_framebuffer() will not be called and conflicted surface views will not be detected. To fix this, also check for conflicted surface views when setting sampler views. If there is any conflicted surface views, enable the framebuffer dirty bit so that the framebuffer emit code has a chance to create a backed surface view for the conflicted surface view. Fix cinebench-r11-test regression. Reviewed-by: Brian Paul <[email protected]>
* svga: update driver for version 10 GPU interfaceBrian Paul2015-09-0264-2369/+8655
| | | | | | | | | | | | | | | | | This is a squash commit of roughly two years of development work. Authors include: Brian Paul Charmaine Lee Thomas Hellstrom Jakob Bornecrantz Sinclair Yeh Mingcheng Chen Kai Ninomiya MengLin Wu The driver supports OpenGL 3.3. Signed-off-by: Brian Paul <[email protected]>
* svga: add new version 10 device command prototypesBrian Paul2015-09-021-0/+333
| | | | Signed-off-by: Brian Paul <[email protected]>
* svga: add new svga_streamout.h fileBrian Paul2015-09-021-0/+50
| | | | Signed-off-by: Brian Paul <[email protected]>
* svga: add new svga_state_tgsi_transform.c fileBrian Paul2015-09-021-0/+293
| | | | Signed-off-by: Brian Paul <[email protected]>
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