| Commit message (Collapse) | Author | Age | Files | Lines |
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needed for asic specific opcodes
Signed-off-by: Alex Deucher <[email protected]>
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The usage of macro V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR was
introduced by commit 323ef3a1f07ba4333dadebab571ddcd49d95f45c but the
macro is undefined. Disable this case to fix the build for now.
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Fixes SCons build.
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Point smoothing requires rasterization rules to be set to OGL.
Sorry for the extra noise caused by the header update.
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Left in the code as a marker of what NVIDIA do, just in case we need
to do this some day.
Signed-off-by: Ben Skeggs <[email protected]>
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Fixes a PT_NOT_PRESENT error cause by:
- allocating in VRAM
- emitting GART relocs to 0x17bc/0x17c0, moving the buffer
- telling the bufmgr that the buffer should be in VRAM when we use it,
but not correcting the value sent to 0x17bc/0x17c0.
Signed-off-by: Ben Skeggs <[email protected]>
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If last instruction is an CF_INST_ALU we don't need to emit an
additional CF_INST_POP for stack clean up after an IF ELSE ENDIF.
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tgsi_helper_copy is used on several occasions to copy a temporary result
into the real destination register to emulate writemasks for OP3 and
reduction operations. According to R600 ISA that's unnecessary.
This patch fixes this use for MAD, CMP and DP4.
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Signed-off-by: Tilman Sauerbeck <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
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This avoid any issue when context is free and we still try to
access fence through radeon structure.
Signed-off-by: Jerome Glisse <[email protected]>
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If you want to enable noop set GALLIUM_NOOP=1 as an env variable.
You need first to enable noop wrapping for your driver see change
to src/gallium/targets/dri-r600/ in this commit as an example.
Signed-off-by: Jerome Glisse <[email protected]>
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Performance++.
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still a bit of work to do, the winsys gen setting is a bit of a hack.
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https://bugs.freedesktop.org/show_bug.cgi?id=32912
The fix is to call update_derived_state before user buffer uploads.
I've also moved some code around.
Unfortunately, there are still some ZMASK-related bugs which cause
misrendering, i.e. flushing doesn't always work and glean/fbo fails.
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The motivation behind this rework is to get some speed by reducing
CPU overhead. The performance increase depends on many factors,
but it's measurable (I think it's about 10% increase in Torcs).
This commit replaces libdrm's radeon_cs_gem with our own implemention.
It's optimized specifically for r300g, but r600g could use it as well.
Reloc writes and space checking are faster and simpler than their
counterparts in libdrm (the time complexity of all the functions
is O(1) in nearly all scenarios, thanks to hashing).
(libdrm's radeon_bo_gem is still being used in the driver.)
It works like this:
cs_add_reloc(cs, buf, read_domain, write_domain) adds a new relocation and
also adds the size of 'buf' to the used_gart and used_vram winsys variables
based on the domains, which are simply or'd for the accounting purposes.
The adding is skipped if the reloc is already present in the list, but it
accounts any newly-referenced domains.
cs_validate is then called, which just checks:
used_vram/gart < vram/gart_size * 0.8
The 0.8 number allows for some memory fragmentation. If the validation
fails, the pipe driver flushes CS and tries do the validation again,
i.e. it validates only that one operation. If it fails again, it drops
the operation on the floor and prints some nasty message to stderr.
cs_write_reloc(cs, buf) just writes a reloc that has been added using
cs_add_reloc. The read_domain and write_domain parameters have been removed,
because we already specify them in cs_add_reloc.
The space checking has been tested by putting small values in vram/gart_size
variables.
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Occurred because the code assumed that buf->domain would remain
equal to old_domain.
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There are actually applications that profit immensely from this.
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... instead of the next fence to be emitted. This way we have a
chance to reclaim the storage earlier.
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